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參數(shù)資料
| 型號： | MM74HC161SJX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 計(jì)數(shù)器 |
| 中文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 105K |
| 代理商： | MM74HC161SJX |
www.fairchildsemi.com
4
MM74HC161
MM
74HC163
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
43
30
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to RC
30
35
ns
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
29
34
ns
tPHL, tPLH
Maximum Propagation Delay, ENT to RC
18
32
ns
tPHL
Maximum Propagation Delay, Clear to Q or RC
27
38
ns
tREM
Minimum Removal Time, Clear to Clock
10
20
ns
tS
Minimum Set Up Time Clear, Load,
30
ns
Enable or Data to Clock
tH
Minimum Hold Time, Data from Clock
5
ns
tW
Minimum Pulse Width Clock,
16
ns
Clear, or Load
Symbol
Parameter
Conditions
VCC
TA = 25°CTA = 40 to 85°CTA = 55 to 125°C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
2.0V
10
5
4
MHz
Frequency
4.5V
40
27
21
18
MHz
6.0V
45
32
25
21
MHz
tPHL
Maximum Propagation
2.0V
100
215
271
320
ns
Delay, Clock to RC
4.5V
32
43
54
64
ns
6.0V
28
37
46
54
ns
tPLH
Maximum Propagation
2.0V
88
175
220
260
ns
Delay, Clock to RC
4.5V
18
35
44
52
ns
6.0V
15
30
37
44
ns
tPHL
Maximum Propagation
2.0V
95
205
258
305
ns
Delay, Clock to Q
4.5V
30
41
52
61
ns
6.0V
26
35
44
52
ns
tPLH
Maximum Propagation
2.0V
85
170
214
253
ns
Delay, Clock to Q
4.5V
17
34
43
51
ns
6.0V
14
29
36
43
ns
tPHL
Maximum Propagation
2.0V
90
195
246
291
ns
Delay, ENT to RC
4.5V
28
39
49
58
ns
6.0V
24
33
42
49
ns
tPLH
Maximum Propagation
2.0V
80
160
202
238
ns
Delay, ENT to RC
4.5V
16
32
40
48
ns
6.0V
14
27
34
41
ns
tPHL
Maximum Propagation
2.0V
100
220
275
325
ns
Delay, Clear to RC
4.5V
32
44
55
66
ns
6.0V
28
37
47
55
ns
tPHL
Maximum Propagation
2.0V
100
210
260
315
ns
Delay, Clear to Q
4.5V
32
42
52
63
ns
6.0V
28
36
45
54
ns
tREM
Minimum Removal
2.0V
125
158
186
ns
Time Clear to Clock
4.5V
25
32
37
ns
6.0V
21
27
32
ns
tS
Minimum Setup
2.0V
150
190
225
ns
Time Clear or Data
4.5V
30
38
45
ns
to Clock
6.0V
26
32
38
ns
tS
Minimum Setup
2.0V
135
170
200
ns
Time Load
4.5V
27
34
41
ns
to Clock
6.0V
23
29
35
ns
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