參數(shù)資料
型號(hào): MM74HC02SJ
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 0K
描述: IC GATE NOR QUAD 2-INP 14-SOP
標(biāo)準(zhǔn)包裝: 47
系列: 74HC
邏輯類型: 或非門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 5.2mA,5.2mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 15ns @ 6V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 管件
1983 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HC02 Rev. 1.3.0
4
MM74HC02
Quad
2-Input
NOR
Gate
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified)
Note:
4. CPD determines the no load dynamic power consumption, PD = CPD VCC
2 f + I
CC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol
Parameter
Conditions
Typ.
Guaranteed
Limit
Units
tPHL, tPLH
Maximum Propagation Delay
8
15
ns
Symbol
Parameter
VCC (V) Conditions
TA = 25°C
TA = –40°C
to 85°C
TA = –55°C
to 125°C
Units
Typ.
Guaranteed Limits
tPHL, tPLH
Maximum
Propagation Delay
2.0
45
90
113
134
ns
4.5
9
18
23
27
6.0
8
15
19
23
tTLH, tTHL
Maximum Output
Rise and Fall Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
CPD
Power Dissipation
Capacitance(4)
(per gate)
20
pF
CIN
Maximum Input
Capacitance
510
10
pF
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