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參數(shù)資料
| 型號： | MM70C97J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | CMOS SERIES, 6-BIT DRIVER, TRUE OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MM70C97J |
AC Electrical Characteristics TA e 25 C CL e 50 pF unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0 tpd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95MM80C95 MM70C97MM80C97
VCC e 5V
60
100
ns
VCC e 10V
25
40
ns
MM70C96MM80C96 MM70C98MM80C98
VCC e 5V
70
150
ns
VCC e 10V
35
75
ns
tpd0 tpd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95MM80C95 MM70C97MM80C97
VCC e 5V CL e 150 pF
85
160
ns
VCC e 10V CL e 150 pF
40
80
ns
MM70C96MM80C96 MM70C98MM80C98
VCC e 5V CL e 150 pF
95
210
ns
VCC e 10V CL e 150 pF
45
110
ns
t1H t0H
Delay from Disable Input to High Impedance
RL e 10k CL e 5pF
State (from Logical ‘‘1’’ or Logical ‘‘0’’)
MM70C95MM80C95
VCC e 5V
80
135
ns
VCC e 10V
50
90
ns
MM70C96MM80C96
VCC e 5V
100
180
ns
VCC e 10V
70
125
ns
MM70C97MM80C97
VCC e 5V
70
125
ns
VCC e 10V
50
90
ns
MM70C98MM80C98
VCC e 5V
90
170
ns
VCC e 10V
70
125
ns
tH1 tH0
Delay from Disable Input to Logical ‘‘1’’ Level
RL e 10k CL e 50 pF
(from High Impedance State)
MM70C95MM80C95
VCC e 5V
120
200
ns
VCC e 10V
50
90
ns
MM70C96MM80C96
VCC e 5V
130
225
ns
VCC e 10V
60
110
ns
MM70C97MM80C97
VCC e 5V
95
175
ns
VCC e 10V
40
80
ns
MM70C98MM80C98
VCC e 5V
120
200
ns
VCC e 10V
50
90
ns
CIN
Input Capacitance
Any Input (Note 2)
50
pF
COUT
Output Capacitance TRI-STATE
Any Output (Note 2)
11
pF
CPD
Power Dissipation Capacitance
(Note 3)
60
pF
AC Parameters are guaranteed by DC correlated testing
Truth Tables
MM70C95MM80C95
Disable
Input
Output
DIS1
DIS2
00
0
00
1
0
1
X
H-z
1
0
X
H-z
1
X
H-z
MM70C96MM80C96
Disable
Input
Output
DIS1
DIS2
00
0
1
00
1
0
1
X
H-z
1
0
X
H-z
1
X
H-z
MM70C97MM80C97
Disable
Input
Output
DIS4
DIS2
00
0
00
1
X
1
X
H-z
1
X
H-z
Output 5–6 only
Output 1–4 only
X e Irrelevant
MM70C98MM80C98
Disable
Input
Output
DIS4
DIS2
00
0
1
00
1
0
X
1
H-z
1
X
H-z
3
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|---|---|
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