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參數(shù)資料
| 型號： | MM24164WMN1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Kbit Serial I2C BUS EEPROM |
| 中文描述： | 16千位串行I2C總線的EEPROM |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 135K |
| 代理商： | MM24164WMN1T |
7/21
M24164
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 4 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
WC
DATA IN 3
AI02804
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK
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