參數(shù)資料
型號(hào)： ML9208A-XXGA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 5 X 7 DOT CHARACTER FLUORESCENT DSPL CTRL, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁(yè)數(shù)： 6/35頁(yè)
文件大小： 632K
代理商： ML9208A-XXGA
FEDL9208A-02
ML9208A-xx
14/35
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the
CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the
CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the
CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
tDOFF
B0
LSB
CS
CP
DA
B1B2B3B4B5B6B7
B0B1B2B3B4B5B6B7
MSB
1st byte
LSB
MSB
2nd byte
When data is written
to DCRAM*
Command and address
data
tCSH
B0B1B2B3B4B5B6B7
LSB
MSB
2nd byte
Character code data of
the next address
Character code data
*
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally
incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Reset Function
Reset is executed when the
RESET pin is set to “L”, (when turning power on, for example) and initializes all
functions.
Initial status is as follows.
Address of each RAM address “00”H
Data of each RAM All contents are undefined
General output port All general output ports go “Low”
Display digit 16 digits
Contrast adjustment 0/16
All display lights ON or OFF OFF mode
Segment output All segment outputs go “Low”
AD output All AD outputs go “Low”
Please set again according to “Setting Flowchart” after reset.
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