參數(shù)資料
型號(hào)： ML9042-01DVWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
封裝： DIE-233
文件頁(yè)數(shù)： 34/58頁(yè)
文件大?。?/td> 558K
代理商： ML9042-01DVWA
FEDL9042-01
OKI Semiconductor
ML9042-xx
4/58
PIN DESCRIPTIONS
Symbol
Description
RW/SI
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
The pin to input data in the Serial l/F Mode. Each instruction code and each data are
read in by the rising edge of the E/SHTB signal.
RS0/CSB, RS1
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting
the RSo/CSB pin to “L” allows the I/F to be provided.
E/SHTB
The input pin for data input/output between the CPU and the ML9042 and for
activating instructions in the Parallel l/F Mode.
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the
DB0(SO) pin is synchronized to the falling edge of the shift clock.
DB0(SO) to DB3
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag
& address and data are output synchronized to the falling edge of the E/SHTB signal.
These pins remain pulled up when data is not output.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
DB4 to DB7
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
OSC1
OSC2
OSCR3
OSCR5
The clock oscillation pins required for LCD drive signals and the operation of the
ML9042 by instructions sent from the CPU.
To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2
pins should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open.
To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open.
To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open.
(The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042,
and the OSC1 pin can be open.)
COM1 to COM17
The LCD common signal output pins.
For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For
1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16
duty, a non-selectable voltage waveform is output via COM17.
SEG1 to SEG100
The LCD segment signal output pins.
RS1
RS0/CSB
Name of register
H
Data register
H
L
Instruction register
L
Expansion Instruction register
相關(guān)PDF資料
PDF描述
ML9042-11DVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
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ML9042-11CVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
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