參數(shù)資料
型號(hào)： ML9042-01DVWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
封裝： DIE-233
文件頁(yè)數(shù)： 29/58頁(yè)
文件大?。?/td> 558K
代理商： ML9042-01DVWA
FEDL9042-01
OKI Semiconductor
ML9042-xx
35/58
N
ABE
Number of
display lines
Font size
Duty
Number of
biases
Number of
common signals
0
1
5
× 8
1/8
4
8
0
1
5
× 8
1/9
4
9
1
0
2
5
× 8
1/16
5
16
1
2
5
× 8
1/17
5
17
Note:
The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270
kHz.
7) CGRAM Address Setting
RS1
1
RS0
0
R/
W
0
DB7
0
DB6
1
DB5
C5
DB4
C4
DB3
C3
DB2
C2
DB1
C1
DB0
C0
Instruction code:
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1
1
RS0
0
R/
W
0
DB7
1
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the
DDRAM.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS1
1
RS0
1
R/
W
0
DB7
E7
DB6
E6
DB5
E5
DB4
E4
DB3
E3
DB2
E2
DB1
E1
DB0
E0
Instruction code:
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
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