參數(shù)資料
型號(hào)： ML87V3116
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 顯示控制器
英文描述： DOT MAT LCD DSPL CTLR, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 6/46頁
文件大?。?/td> 273K
代理商： ML87V3116
PEDL87V3116-02
OKI Semiconductor
ML87V3116
14/47
[Control Registers]
CPPOL
: Synchronous polarity selection for CP and output data, 1 bit (write/read)
“0”: Synchronizes on the rising edge of CP, “1”: Synchronizes on the falling edge of CP
HLCYC
: HST/LDP cycle (units of the number of CP clocks), 11 bits (write/read)
HST1POL
: HST1 pulse polarity selection, 1 bit (write/read)
“0”: Positive pulse, “1”: Negative pulse (same for the following)
HST1POS
: HST1 pulse position, 11 bits (write/read)
HST2POL
: HST2 pulse polarity selection, 1 bits (write/read)
HST2POS
: HST2 pulse position, 11 bits (write/read)
LDP1POL
: LDP1 pulse polarity selection, 1 bits (write/read)
LDP1ST
: LDP1 pulse's front edge position, 11 bits (write/read)
LDP1ED
: LDP1 pulse's rear edge position, 11 bits (write/read)
LDP2POL
: LDP2 pulse polarity selection, 1 bits (write/read)
LDP2ST
: LDP2 pulse's front edge position, 11 bits (write/read)
LDP2ED
: LDP2 pulse's rear edge position, 11 bits (write/read)
LDP3POL
: LDP3 pulse polarity selection, 1 bits (write/read)
LDP3ST
: LDP3 pulse's front edge position, 11 bits (write/read)
LDP3ED
: LDP3 pulse's rear edge position, 11 bits (write/read)
LDP4POL
: LDP4 pulse polarity selection, 1 bits (write/read)
LDP4ST
: LDP4 pulse's front edge position, 11 bits (write/read)
LDP4ED
: LDP4 pulse's rear edge position, 11 bits (write/read)
VFCYC
: FDP cycle (units of the number of lines), 10 bits (write/read)
FDP1POL
: FDP1 pulse polarity selection, 1 bits (write/read)
FDP1ST
: FDP1 pulse's front edge position, 10 bits (write/read)
FDP1ED
: FDP1 pulse's rear edge position, 10 bits (write/read)
FDP2POL
: FDP2 pulse polarity selection, 1 bits (write/read)
FDP2ST
: FDP2 pulse's front edge position, 10 bits (write/read)
FDP2ED
: FDP2 pulse's rear edge position, 10 bits (write/read)
FDP3POL
: FDP3 pulse polarity selection, 1 bits (write/read)
FDP3ST
: FDP3 pulse's front edge position, 10 bits (write/read)
FDP3ED
: FDP3 pulse's rear edge position, 10 bits (write/read)
FDP2MIX
: Positive pulse AND synthesis between FDP2 and LDP4, 1 bit (write/read)
“0”: Without synthesis, “1”: With synthesis
FDP3MIX
: Positive pulse OR synthesis between FDP3 and LDP2 bit (write/read)
“0”: Without synthesis, “1”: With synthesis
ACTHST
: Horizontal start position of effective image data, 11 bits (write/read)
ACTHED
: Horizontal end position of effective image data, 11 bits (write/read)
ACTVST
: Vertical start position of effective image data, 10 bits (write/read)
ACTVED
: Vertical end position of effective image data, 10 bits (write/read)
相關(guān)PDF資料
PDF描述
ML87V3116 DOT MAT LCD DSPL CTLR, PQFP176
ML9041-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9041-01BCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
ML9041A-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9042-XXCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
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