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參數(shù)資料
| 型號： | ML87V3116 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | DOT MAT LCD DSPL CTLR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 273K |
| 代理商： | ML87V3116 |
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PEDL87V3116-02
OKI Semiconductor
ML87V3116
13/47
CP
: Data clock
The polarity of CP can be selected.
LDP1-4
: Line drive pulse (4 types)
The pulse cycle is common to LDP1-4, and the pulse width, pulse phase and pulse polarity
can be specified in units of the number of CP clocks.
When in the TV mode, LDP1 is automatically set and used as a HSYNC.
HST1, 2
: Horizontal start signal (2 types)
The pulse width is 1 CP clock, and the pulse cycle (common to two types), pulse phase and
pulse polarity can be specified.
FDP1-3
: Frame drive pulse (3 types)
The frame cycle (common to 3 types), pulse width, pulse phase and pulse polarity can be
specified in units of the number of lines.
By ANDing FDP2 with LDP4, a frame cycle pulse with a pulse width narrower than one
line can be set.
By ORing FDP3 with FDP2, a drive pulse can be set twice in one frame.
When in the TV mode, FDP1 is automatically set and used as a VSYNC.
FIDF
: Current-alternating drive signal, or field ID signal
A signal that inverts for each frame, or a signal that inverts for each number of specified
lines. In the latter case, the logic at the beginning of a frame is inverted for each frame.
When in the TV mode, FIDF is automatically set so as to invert for each frame, and used as
a field ID signal.
DISP
: Display enable signal
A signal that specifies display ON/OFF
Set the pulse phases of the “HST1, 2” and “LDP1-4” signals using an internal, virtual horizontal synchronous
signal as a reference.
The “FDP1-3” signals are synchronized with this virtual horizontal synchronous signal. Set the pulse phases of
the “FDP1-3” signals using an internal, virtual vertical synchronous signal as a reference.
Set the horizontal and vertical effective periods of output data in the same manner.
These settings can be changed in the TFT-LCD mode. However, the values set are held even after switching to
the TV mode; thus, display can be performed in the original state when returning to the TFT-LCD mode again.
The “LDP2-4,” “HST1, 2” and “FDP2-3” signals can be used as GPIOs if they are not used as synchronous
signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML87V3116 | DOT MAT LCD DSPL CTLR, PQFP176 |
| ML9041-XXACVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
| ML9041-01BCVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175 |
| ML9041A-XXACVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
| ML9042-XXCVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
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