參數(shù)資料
型號： ML87V3104TB
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 顯示控制器
英文描述： 640 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100
文件頁數(shù)： 9/69頁
文件大?。?/td> 444K
代理商： ML87V3104TB
FEDL87V3104-03
OKI Semiconductor
ML87V3104
17/69
3.1.2 LCD control timing
The LCD control timing is determined by the LCP (line clock pulse) signal and the FRP (frame pulse) signal. It is
also possible to set the polarities of these pulses individually.
(7)
(2)
(3)
(1)
(5)
Active display area
(6)
LCP
FRP
Fig. F3.1.2 LCD drive timing
Control registers:
(1) LCPCYC [#05h, #04h]:
(LCP signal period – 1)
In units of a CP clock in the STN color 4-bit mode
In units of 2 CP clocks in the STN color 8-bit mode or 4-bit 2-phase mode
In units of 4 CP clocks in the STN monochrome 4-bit mode
In units of 8 CP clocks in the STN monochrome 8-bit mode or 4-bit 2-phase mode
In units of a CP clock in the TFT color mode
(2) LCPSTA [#07h, #06h]:
LCP start timing, in units of a CP clock
(3) LCPWID
[#07h; bit7-4]: (LCP pulse width – 1), in units of 4
× CP clocks
(4) LCPPOL [#05h; bit7]:
LCP pulse polarity, ‘0’: Positive, ‘1’: Negative
(5) FRPCYC [#09h, #08h]:
FRP signal period, in units of a line, (5)
≥ (6)+2
(6) FRPSTA [#0Bh, #0Ah]:
FRP start timing, in units of a line
(7) FRPWID [#0Bh; bit7-4]: (FRP pulse width – 1), in units of a line
(8) FRPPOL [#09h; bit7]:
FRP pulse polarity, ‘0’: Positive, ‘1’: Negative
Note: The internal memory gets started by setting above registers. These must be set at first after the power
up or the internal memory cannot be accessed.
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