參數(shù)資料
型號: ML87V3104TB
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 顯示控制器
英文描述: 640 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100
文件頁數(shù): 30/69頁
文件大?。?/td> 444K
代理商: ML87V3104TB
FEDL87V3104-03
OKI Semiconductor
ML87V3104
36/69
5.2
Address mapping
The ML87V3104 supports a 19-bit byte address for access from the host CPU. The 4M bit display memory and
the 32-byte control registers are mapped to this address.
When accessing the display memory, the bit assignment of the address is determined by the setting of the memory
size. (Fig. F5.2) See the next section for details of the control registers.
7
Host address
018
0
7
0
Page No.
Host data
4 bits/pixel
8 bits/pixel
16 bits/pixel
X=2n+0 X=2n+1
X
1
Y
0
px0
px1
2-pixel packed format
Y address
(v bits)
X address
((u-1) bits)
Effective page No.
(w bits)
7
0
18
0
7
0
X
0
Y
0
px
0
7
Y address
(v bits)
X address
(u bits)
Effective page No.
(w bits)
7
0
18
0
7
0
X
0
Y
0
B
R
1
2
3
5
B
Byte
address
Y address
(v bits)
X address
(u bits)
Effective page No.
(w bits)
B=’0’
B=’1’
5
0
G
1 5
7
0
18
0
7
0
3
0
The number of total address bits = ( w bits ) + ( v bits ) + ( u bits ) = 19 bits (512K Byte)
Fig. F5.2 Display memory address mapping
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