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參數(shù)資料
| 型號： | ML67Q4002LA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33.333 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 645K |
| 代理商： | ML67Q4002LA |
ML674001/ML67Q4002/ML67Q4003
4 Oki Semiconductor
April 2004, Rev 2.0
Direct Memory Access Controller (DMAC)
Two-channel direct memory access controller (DMAC) which transfers data
between memory and memory, between I/O and memory, and between I/O
and I/O.
External Memory Controller
Controls access of externally connected devices such as ROM (FLASH), SRAM,
SDRAM (EDO DRAM), I/O devices and external FLASH memory.
1. ROM (FLASH) access function: 1 bank (supports up to 16 MBytes)
Supports 16-bit devices
Supports FLASH memory: Byte write (can be written only by IF equivalent
to SRAM).
In ML67Q4002/4003, control internal FLASH access.
Congurable access timing.
2. SRAM access function : 1 bank
Supports 16-bit devices
Supports asynchronous SRAM
Congurable access timing.
3. DRAM access function : 1 bank
Supports 16-bit devices
Supports EDO-DRAM/SDRAM: Simultaneous connections to EDO-DRAM
and SDRAM cannot be made.
Congurable access timing.
4. External I/O access function: 2 banks
Supports 8-bit/16-bit access: Independent conguration for each bank.
Each bank has two chip selects: XIOCS_N[3:0].
Supports external wait input: XWAIT
Access timing congurable for bank independently.
GPIO
42-bit parallel port (four 8-bit ports and one 10-bit port).
1. Number of
channels:
2 channels
2. Channel priority
level:
Fixed mode:
Channel priority level is always
xed (channel 0 >1).
Roundrobin:
Priority level of the channel
requested for transfer is kept
lowest.
3. Maximum number
of transfers:
65,536 per DMA operation.
4. Data transfer size: Byte (8 bits), Half-word (16 bits), Word (32 bits)
5. Bus request
system:
Cycle steal
mode:
Bus request signal is asserted for
each DMA transfer cycle.
Burst mode:
Bus request signal is asserted until
all transfers of transfer cycles are
complete.
6. DMA transfer
request:
Software
request:
By setting the software transfer
request bit inside the DMAC, the
CPU starts DMA transfer.
External
request:
DMA transfer is started by exter-
nal request allocated to each
channel.
7. Interrupt request:
Interrupt request is generated in CPU after the end
of DMA transfer for the set number of transfer
cycles, or after the occurrence of an error.
Interrupt request signal is output separately for
each channel.
Interrupt request signal output can be masked for
each channel.
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
Combination port
UART
DMAC, SIO (PLAT-7B)
PWM, XA[23:19], XWR
DRAM control signals etc.
SSIO, I2C, External interrupt signal
1. Input/output selectable at bit level.
2. Each bit can be used as an interrupt source.
3. Interrupt mask and interrupt priority can be set for all bits.
4. The ports are congured as input, immediately after reset.
5. Primary/secondary function of each port can be set independently.
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| ML67Q4003 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:32-bit ARM-Based General-Purpose Microcontroller |
| ML67Q4003-1NNNTCZ03A | 制造商:OKI Semiconductor 功能描述:OKIML67Q4003-1NNNTCZ03A 32-bit ARM Micro 制造商:ROHM Semiconductor 功能描述:RHOML67Q4003-1NNNTCZ03A ML67Q4003-1NNNTC |
| ML67Q4003LA | 制造商:ROHM Semiconductor 功能描述: |
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