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參數(shù)資料
| 型號(hào)： | ML675001TC |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 650K |
| 代理商： | ML675001TC |
ML675001/ML67Q5002/ML67Q5003
12 Oki Semiconductor
April 2004, Rev 2.0
Pin Descriptions
Pin Name
I/O
Description
Primary/
Secondary
Logic
System
RESET_N
I
Reset input
–Negative
BSEL[1:0]
I
Boot device select signal.
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) after reset.
–Positive
CLKMD[1:0]
I
Clock mode inputs. Normally connected to GND.
–
Positive
OSC0
I
Crystal oscillator connection or external clock input.
If used, connect a crystal oscillator (5 MHz to 14 MHz) to OSC0 and OSC1_N.
It is also possible to input a direct clock (5 MHz, 20 MHz to 56 MHz).
––
OSC1_N
O
Oscillation output pin.
When not using a crystal oscillator, leave this pin unconnected.
––
CKO
O
Clock out.
––
CKOE_N
I
Clock out enable.
–
Negative
JTAG Interface
TCK
I
Debugging pin. Normally connect to ground level.
–
TMS
I
Debugging pin. Normally drive at High level.
–
Positive
nTRST
I
Debugging pin. Normally connect to ground level.
–
Negative
TDI
I
Debugging pin. Normally drive at High level.
–
Positive
TDO
O
Debugging pin. Normally leave open.
–
Positive
General-purpose I/O Interface
PIOA[7:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Primary
Positive
PIOB[7:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Primary
Positive
PIOC[7:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Primary
Positive
PIOD[7:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Note that enabling the DRAM controller by asserting the DRAME_N inputs permanently con-
gures PIOD[7:0] for their secondary functions, making them unavailable for use as port
pins.
Primary
Positive
PIOE[9:0]
I/O
General-purpose port. Not available for use as port pins when secondary functions are in
use.
Primary
Positive
External Bus Interface (Global)
XA[23:19]
O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM. After
a reset, these pins are congured for their primary function PIOC[6:2].
Secondary
Positive
XA[18:0]
O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM.
–
Positive
XD[15:0]
I/O
Data bus to external RAM, external ROM, external I/O banks, and external DRAM.
–
Positive
External Bus Interface (ROM, SRAM and I/O)
XROMCS_N
O
ROM bank chip select.
–
Negative
XRAMCS_N
O
SRAM bank chip select.
–
Negative
XIOCS_N[0]
O
I/O chip select 0.
–
Negative
XIOCS_N[1]
O
I/O chip select 1.
–
Negative
XIOCS_N[2]
O
I/O chip select 2.
–
Negative
BSEL[1]
BSEL[0]
Boot device
LL
Internal Flash (External ROM for ML675001)
LH
External ROM
H*
Boot ROM (* = don’t care)
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