參數(shù)資料
型號(hào)： ML6510CQ-130
英文描述： Series Programmable Adaptive Clock Manager (PACMan⑩)
中文描述： 系列可編程自適應(yīng)時(shí)鐘管理器（吃豆⑩）
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 603K
代理商： ML6510CQ-130
8
ML6510
FUNCTIONAL DESCRIPTION
Micro Linear’s ML6510 is the first clock chip to use a
feedback mechanism to adaptively (on a real time basis),
eliminate clock skew in high speed personal computer
and workstation system designs. Figure 1 shows a basic
configuration of the ML6510 in a system. The skew
problem results due to the delaying of clock signals in the
system, as shown in Figure 2. Clock skew results from
variation in factors like trace length, PCB trace
characteristics, load capacitance, parasitic capacitance,
temperature and supply variations, etc. Figure 2 shows a
representation of the clock skew problem from a timing
perspective. It shows a worst case example where the
clock signal is delayed so much that its rising edge
completely misses the data it is intended to strobe.
Using a clock deskew mechanism, this problem can be
eliminated and the strobe with the appropriate setup and
hold times with respect to the data bus can be generated.
The ML6510 has eight deskew buffers, each with its own
independent the reflection and error correction circuit.
The deskew buffer eliminates skew by using the reflection
from a remote chip to measure the clock error and then
corrects it by generating the appropriate skew to the clock
output to compensate.
Eight individually deskewed copies of the clock are
provided by the ML6510.
The deskew buffers compensate internally for board-level
skew caused by the PCB trace length variations and
device load variations. This is accomplished by sensing
the round trip delay via a reflected signal, and then
delaying or advancing the clock edge so that all 8 output
clocks arrive at their loads in phase. Each of the eight
clock lines can have any length PCB trace (up to 5ns each
way or 1/4th of the output clock period, whichever is
smaller) and the device loads can vary from line to line.
The ML6510 will automatically compensate for these
variations, keeping the device load clocks in phase.
Although ML6510 will compensate for skew caused by
loading, excessive capacitive loading can cause rise/fall
time degradation at the load. Cascading one ML6510 to
another ML6510 should be done using the PECL reference
clock outputs, to minimize part-to-part skew.
CLOCK REGENERATION
The programmable adaptive clock deskew can function in
a clock regeneration mode to assist in building clock trees
or to expand the number of deskewed clock lines. In this
mode, it has the ability to do clock multiplication or
division as well, while maintaining low skew between
WRITE
SIGNAL
CLOCK AT
REMOTE CHIP
DATA AT
REMOTE CHIP
WRITE
SIGNAL
CLOCK AT
REMOTE CHIP
DATA AT
REMOTE CHIP
DATA
DATA
tS
tH
Figure 2. The Skew Problem.
CPU
MICRO LINEAR
ML6510
CLOCK CHIP
REMOTE
CHIP
CLOCK #0
FEEDBACK #0
CLOCK #1
FEEDBACK #1
CLOCK #7
FEEDBACK #7
DATA
CLOCK
GENERATOR
CLOCK IN
Figure 1. Basic System Configuration Using the ML6510.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML6510CQ80 制造商:Rochester Electronics LLC 功能描述:- Bulk
ML6510CQ-80 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩)
ML6516244 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CR 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CT 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
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