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參數(shù)資料
| 型號(hào)： | ML6510CQ-130 |
| 英文描述： | Series Programmable Adaptive Clock Manager (PACMan⑩) |
| 中文描述： | 系列可編程自適應(yīng)時(shí)鐘管理器（吃豆⑩） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 603K |
| 代理商： | ML6510CQ-130 |
5
ML6510
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).
t
R
Rise time, LOAD [0-7] output
0.8
→
2.0V, 80MHz
150
1500
ps
t
F
Fall time, LOAD [0-7] output
2.0
→
0.8V, 80MHz
150
1500
ps
f
IN
Input frequency, CLK
IN
pin
10
80
MHz
f
OUT
Output frequency , CLK [0-7]
output
ML6510-80
10
80
MHz
ML6510-130 (Note 2)
10
130
MHz
f
VCO
PLL VCO operating frequency
80
160
MHz
DC
Output duty cycle
Measured at device load, at 1.5V
40
60
%
t
JITTER
Output jitter
Cycle-to-cycle
75
ps
Peak-to-peak
150
ps
t
LOCK
PLL and deskew lock time
After programming is complete
11
ms
SKEW CHARACTERISTICS
All skew measurements are made at the load, at 1.5V threshold each output load can vary independently
within the specified range for a generic load (see Load Conditions section).
t
SKEWR
Output to output rising
edge skew, all clocks
500
ps
t
SKEWF
Output to output
falling edge skew
Output clock frequency
≥
50MHz
1.5
ns
t
SKEWIO
CLK
IN
input to any
LOAD [0-7] output
rising edge skew
N = M = 0
600
ps
N
≥
2, M
≥
2
1.25
ns
t
RANGE
Round trip delay CLKX to FBX
pin; output CLK period = t
CLK
Output frequency < 50MHz
Output frequency
≥
50MHz
0
0
10
ns
t
CLK
/2
t
SKEWB
Output-to-output rising
edge skew, between matched
loads
Providing first (see LOAD
conditions) order matching
order matching between outputs
250
ps
PART-TO-PART SKEW CHARACTERISTICS
Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock
input pins of another ML6510.
t
PP1
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1 and
N = 0, M = 0; RCLK outputs to
CLK
IN
inputs distance less than 2"
1
ns
t
PP2
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1 and
N
≥
2, M
≥
2; RCLK outputs to
CLK
IN
inputs distance less than 2"
1
ns
PROGRAMMING TIMING CHARACTERISTICS
t
RESET
RESET
assertion pulse
width
50
ns
t
A1
AUX mode MCLK high time
2000
ns
t
A2
AUX mode MCLK low time
2000
ns
t
A3
AUX mode MD
OUT
data
hold time
10
ns
t
A4
AUX mode MD
OUT
data
setup time
10
ns
t
A5
AUX mode MCLK period
5000
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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