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參數(shù)資料
| 型號： | ML6401CS-1 |
| 英文描述： | 8-Bit 20 MSPS A/D Converter |
| 中文描述： | 8位20 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 554K |
| 代理商： | ML6401CS-1 |
4
ML6401
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Characteristics
Maximum CLK Input Frequency
20
25
MHz
Clock Duty Cycle
CLK = 13.5MHz
40
60
%
t
PWH
CLK
≤
20MHz
25
ns
t
PWL
CLK
≤
20MHz
25
ns
Analog To Digital Converter Inputs — CLK
Low Level Input Voltage
V
IL
0
0.8
V
High Level Input Voltage
V
IH
2.4
VDD
D
V
Low Level Input Current
V
IL
= 0.1V
–5
+5
μ
A
High Level Input Current
V
IH
= VDD
D
– 0.1V
–5
+5
μ
A
Input Capacitance
4.0
pF
Timing — Digital Outputs (C
L
= 15pF, I
OL
= 2mA, R
L
= 2k
, f
CLK
= 20MHz)
Sampling Delay
t
DS
5
ns
Output Hold Time
t
HO
4
12
10
ns
Output Delay Time
t
DO
5
18
30
ns
Three-State Delay Time — Output Enable
10
25
ns
Three-State Delay Time — Output Disable
10
20
ns
Analog To Digital Converter Outputs — Digital
Low Level Output Voltage
I
OL
= 2mA
0
0.6
V
High Level Output Voltage
I
OH
= 2mA
2.4
VCC
O
V
Output Current in Three-State Mode
–20
+20
μ
A
Supplies
Analog, Digital & Output Supply Voltage
4.5
5.5
V
Analog Supply Current
Static
26
34
mA
Digital Supply Current
f
CLK
= 20MHz
10
15
mA
Output Supply Current
f
CLK
= 20MHz, C
L
= 0pF
4
10
mA
(V
IN
+) – (V
IN
–)
CLK
D0 TO D7
SAMPLE
OUT
N
N+1
N+2
N+3
N+4
N–3
N–2
N–1
N
N+1
t
DS
t
PWH
t
PWL
t
HO
t
DO
TIMING DIAGRAM
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
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