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參數(shù)資料
| 型號(hào)： | ML2039CP |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 1-BIT, DSP-NUM CONTROLLED OSCILLATOR, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | ML2039CP |
ML2039
7
The ML2039 has a clock output that can be used to drive
other external devices. The CLK OUT output is a buffered
output from the oscillator which runs at one half the
frequency of CLK IN.
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on S DATA IN is clocked
into a 16-bit shift register on falling edges of the serial
shift clock, S CLK. The LSB should be shifted in first and
the MSB last as shown in Timing Diagram 1. The data that
has been shifted into the shift register is loaded into a 16-
bit data latch on the falling edge of S ENABLE. To insure
that true data is loaded into the data latch from the shift
register, the S ENABLE falling edge should occur before
FUNCTIONAL DESCRIPTION (Continued)
the S CLK transitions high to low. S ENABLE should be
high while shifting data into the shift register. Note that
all data is entered and latched on edges, not levels, of S
CLK and S ENABLE.
Upon power up, the data in the latch is indeterminate. It
is therefore recommended to initialize the frequency data
as part of a power up routine.
POWER SUPPLIES
The ML2039 is powered from 5V (VCC) and is referenced
to GND. It is recommended that the power supply to the
device should be bypassed by placing decoupling
capacitors from VCC to GND as physically close to the
device as possible.
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