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參數(shù)資料
| 型號： | ML1I-67203V-65/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 2K X 9 OTHER FIFO, 65 ns, CDIP28 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 145K |
| 代理商： | ML1I-67203V-65/883 |
L 67203/L 67204
MATRA MHS
Rev. C (10/11/94)
1
Introduction
The L67203/204 implement a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the MHS FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin resets the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eigh transistors (8 T) memory cell and
fabricated with the state of the art 1.0
m lithography
named SCMOS, the L 67203/204 combine an extremely
low standby supply current (typ = 1.0
A) with a fast
access time at 55 ns over the full temperature range. All
versions offer battery backup data retention capability
with a typical power consumption at less than 5
W.
For military/space applications that demand superior
levels of performance and reliability the L 67203/204 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D First-in first-out dual port memory
D Single supply 3.3 ± 0.3 volts
D 2048 × 9 organisation (L 67203)
D 4096 × 9 organisation (L 67204)
D Fast access time
Commercial, industrial automotive and military :
55, 60, 65 ns
D Wide temperature range : – 55 °C to + 125 °C
D 67203L/204L low power
67203V/204V very low power
D Fully expandable by word width or depth
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
D Bi-directional applications
D Battery back-up operation 2 V data retention
D TTL compatible
D High performance SCMOS technology
2K
× 9 & 4K × 9 / 3.3 Volts CMOS Parallel FIFO
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