參數(shù)資料
型號: MK74CG117BFT
元件分類: 時鐘產(chǎn)生/分配
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁數(shù): 1/7頁
文件大?。?/td> 157K
代理商: MK74CG117BFT
MK74CG117B
MDS 74CG117B A
1
Revision 041604
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
16 Output Low Skew Clock Generator
Description
The MK74CG117B is a monolithic CMOS high speed,
low-skew clock driver that includes an on-chip PLL.
Ideal for communications and other systems that
require a large number of high-speed clocks, the
unique combination of PLL and 16 low-skew outputs
can eliminate oscillators and low skew buffers from
systems.
The device has a number of built in multipliers, making
it possible to run from one inexpensive, low frequency
crystal, and produce high frequency clock outputs.
Another selection allows the chip to run as a divider,
dividing the input clock by two (or 4 using the mode
select).
The device also has a buffered reference output,
allowing multiple devices to be easily driven from one
clock source.
Features
48-pin SSOP (300 mil) package
On-chip PLL generates output clocks up to 100 MHz
from a simple crystal or clock input
16 low-skew outputs
Output skew less than 250 ps on rising edges
Ability to configure as
–16 clocks at full frequency
–12 at full and 4 at half frequency
–8 at full and 8 at half frequency
Tri-state mode for Output Enable function
3.3 V ±5% supply voltage
Industrial temperature version available
Block Diagram
Clock
Synthesis
and Mode
Select
Circuitry
S2:0
M1:0
REF
3
GND
VDD
Crystal
Ocsillator
X1/ICLK
X2
The crystal requires external capacitors for
accurate tuning of the clock
2
9
Crystal or
clock input
10
Clock 16
Clock 2
Clock 1
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