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參數(shù)資料
| 型號： | MK74CG117FLF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 69K |
| 代理商： | MK74CG117FLF |
MDS 74CG117 D
1
Revision 041502
Integrated Circuit Systems 525 Race Street. San Jose CA95126 (408)295-9800tel www.icst.com
MK74CG117
16 Output Low Skew Clock Generator
48 pin SSOP (300 mil) package
On-chip PLL generates output clocks up to
100 MHz from a simple crystal or clock input
16 low skew outputs
Output skew less than 250 ps on rising edges
Ability to configure as
- 16 clocks at full frequency
- 12 at full and 4 at half frequency
- 8 at full and 8 at half frequency
Tri-state mode for Output Enable function
3.3 V±5% supply voltage
Industrial temperature version available
The MK74CG117 is a monolithic CMOS high speed,
low-skew clock driver that includes an on-chip PLL.
Ideal for communications and other systems that
require a large number of high-speed clocks, the
unique combination of PLL and 16 low-skew outputs
can eliminate oscillators and low skew buffers from
systems.
The device has a number of built in multipliers, making
it possible to run from one inexpensive, low frequency
crystal, and produce high frequency clock outputs.
Another selection allows the chip to run as a divider,
dividing the input clock by two (or 4 using the mode
select).
The device also has a buffered reference output,
allowing multiple devices to be easily driven from one
clock source.
Block Diagram
Description
Features
Crystal
Oscillator
Clock
Synthesis
and Mode
Select
Circuitry
Output
Buffer
Output
Buffer
Clock 2
Clock 1
Output
Buffer
3
S2:0
Crystal or clock
input
X1/ICLK
X2
REF
Output
Buffer
Clock 16
2
M1:0
9
VDD
10
GND
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