參數(shù)資料
型號: MK68901
廠商: 意法半導(dǎo)體
英文描述: Multifunction Peripheral(多功能外圍電路)
中文描述: 多功能外圍(多功能外圍電路)
文件頁數(shù): 9/33頁
文件大?。?/td> 313K
代理商: MK68901
Figure 11 b :
Daisy Chaining.
Each interrupt channel responds with a discrete 8-
bit vectorwhen acknowledged. The upper four bits
of thevector are set by writing the upper four bits of
the VR. The four low order bits (bit 3-bit 0) are ge-
nerated by the interrupting channel.
To acknowledgeaninterrupt, IACKgoeslow, theIEI
input must golow (orbe tied low) and the MK68901
MFPmust have an acknowledgeable interrupt pen-
ding. The Daisy Chaining capability (figure 11) re-
quires that allpartsinachainhave acommon IACK.
Whenthe commonIACK goes low, all partsfreeze
and prioritize interrupts in parallel. Then priority is
passed down the chain, via IEI and IEO, until a part
which has a pending interrupt is reached. The part
with thepending interrupt,passesavector,doesnot
propagate IEO, and generates DTACK.
Figure 9 describes the 16prioritized interrupt chan-
nels.Aschown,General Purpose Interrupt7hasthe
highestpriority, whileGeneral Purpose Interrupt0 is
assignedthe lowestpriority. Each ofthesechannels
may be reprioritized, in effect, by selectively ma-
sking interrupts under software control. The binary
numbers under ”channel” correspond to the modi-
fied bits IV3, IV2, IV1 and IV0, respectively, of the
Interrupt Vector for each channel (see figure 6).
Each channel has an enable bit contained in IERA
or IERB,a pending latchcontained inIPRAorIPRB,
a mask bit contained in IMRA or IMRB, and an in–
servicelatch contained inISRA or ISRB. Additional-
ly, the eight General Purpose Interrupts each have
an edge bit contained in the Active Edge Register
(AER), a bit to define the line as input or output
contained intheData Direction Register (DDR) and
an I/O bit in the General Purpose Interrupt-I/O Port
(GPIP).
TIMERS
There arefour timerson the MK68901 MFP. Twoof
thetimers (Timer A and Timer B) are full function ti-
mers which can perform the basic delay function
and can also perform event counting, pulse width
measurement, andwaveformgeneration. Theother
two timers (Timer C and Timer D) are delay timers
only.Oneorbothofthese timers canbeusedtosup-
ply the baud rate clocks for the USART. All timers
are prescaler/counter timers with a common inde-
pendent clock input(XTAL1,XTAL2). Inaddition, all
timers have a time-out output, function that toggles
each time thetimer times out.
The four timers are programmed via three Timer
ControlRegisters and four TimerDataRegisters.Ti-
mers Aand Bare controlled by thecontrol registers
TACR and TBCR, respectively (see figure 12), and
by the data registers TADR and TBDR (figure 13).
TimersCand Darecontrolled bythecontrolregister
TCDCR (see figure 14) and two data registers
TCDR and TDDR. Bits in the control registers allow
the selection of operational mode, prescale, and
control white the data registers are used to read the
timer or write into the time constant register. Timer
A and B input pins TAI and TBI, are used for the e-
ventand pulse width modes for timers A and B.
Withthe timer stopped, no counting can occur. The
timer contents will remain unaltered while the timer
isstopped(unless reloaded bywriting theTimerDa-
ta Register), but anyresidual count inthe prescaler
willbe lost.
V000358
MK68901
9/33
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