參數(shù)資料
型號(hào)： MK68901
廠商： 意法半導(dǎo)體
英文描述： Multifunction Peripheral(多功能外圍電路)
中文描述： 多功能外圍（多功能外圍電路）
文件頁(yè)數(shù)： 21/33頁(yè)
文件大?。?/td> 313K
代理商： MK68901
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0Vdc
±
5%, GND = 0Vdc, T
A
= 0
°
C to 70
°
C)
Value
MK68901-4
Min.
50
0
280
50
MK68901-5
Min.
35
0
0
45
Number
Characteristic
Max.
Max.
Unit
Fig.
Note
1
2
3
4
5
6
7
8
9
CS, DS Width High
R/W, A1-A5 Valid to Falling CS (setup)
Data Valid Prior to Falling CLK
CS, IACK Valid to Falling Clock (setup)
CLK Low to DTACK Low
CS, DS or IACK High to DTACK High
CS, DS or IACK High to DTACK Tri-state
DTACK Low to Data Invalid (hold time)
CS, DS or IACK High to Data Tri-state
CS or DS High to R/W, A1-A5 Invalid (hold time)
Data Valid from CS Low
Read Data Valid to DTACK Low (setup)
DTACK Low to DS, CS or IACK High (hold time)
IEI Low to Falling CLK (setup)
IEO Valid from Clock Low (delay)
Data Valid from Clock Low (delay)
IEO Invalid from IACK High (delay)
DTACK Low from Clock High (delay)
IEO Valid from IEI Low (delay)
Data Valid from IEI Low (delay)
Clock Cycle Time
Clock Width Low
Clock Width High
CS, IACK Inactive to Rising Clock (setup)
I/O Minimum Active Pulse Width
IACK Width High
I/O Data Valid from Rising CS or DS
Receiver Ready Delay from Rising RC
Transmitter Ready Delay from Rising TC
Timer Output Low from Rising Edge of CS or DS
(A & B) (reset T
OUT
)
T
OUT
Valid from Internal Timeout
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21,22
21,22
22
21-24
21,22
21-24
21-24
22
21,23,24
21,22
21
21
21-23
23,24
23
23
23, 24
23, 24
24
24
21
21
21
21-23
25
23-24
26
27
28
5
3
220
60
100
180
55
95
0
0
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
0
310
260
3,6
50
0
50
50
0
50
180
300
150
180
100
220
1000
180
300
150
165
100
220
1000
1
1
250
110
110
100
100
2
200
90
90
80
100
2
4,5
T
CLK
ns
ns
ns
2
450
600
600
450
600
600
450
450
ns
29
7
31
2 t
CLK
+ 300
2 t
CLK
+ 300
ns
29
2
32
Timer Clock Low Time
110
90
ns
29
MK68901
21/33
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