
MK50H27
Signalling System 7
Link Controller
SECTION1 - FEATURES
Complete Level 2 Implementationof SS7.
Compatible with 1988 CCITT, AT&T, ANSI,
and Bellcore Signalling System Number 7 link
level protocols.
Optional operation to comply with Japanese
TTC JT-Q703 specificationrequirements
Pin-for-pin and architecturally compatible with
MK50H25 (X.25/LAPD), MK50H29 (SDLC),
and MK50H28(FrameRelay).
System clock rates up to 33 MHz (MK50H27 -
33), or 25 MHz(MK50H27- 25).
Data rate up to 4 Mbps continuous for SS7
protocol processing, 20 Mbps for transparent
HDLC mode, or up to 51 Mbps bursted
(gappeddata clocks, non-continuousdata).
On chip DMA control with programmable burst
length.
DMA transfer rate of up to 13.3Mbytes/sec us-
ing optional 5 SYSCLK DMA cycle (150 nS) at
33 MHzSYSCLK.
BufferManagementincludes:
- InitializationBlock
- SeparateReceive and Transmit Rings
- VariableDescriptor Ring and Window Sizes.
Selectable BEC or PCR retransmission meth-
ods, includingforced retransmission for PCR.
Handles all 7 SS7 Timers, plus the additional
Signal Unit intervaltimers for JapaneseSS7.
Handles all SS7 frame formatting:
- Zerobit insert and delete
- FCS generationand detection
- Framedelimiting with flags
Programmable minimum Signal Unit spacing
(number of flags betweenSU’s)
Handles all sequencingand link control.
SelectableFCS of 16 or 32 bits.
Testing Facilities:
- InternalLoopback
- SilentLoopback
- OptionalInternalData Clock Generation
- Self Test.
Programmablefor full or half duplexoperation
Programmable Watchdog Timers for RCLK
and TCLK(to detectabsenceof data clocks)
Available in 52 pin PLCC, 84 pin PLCC(for use
with external ROM),or 48pin DIP packages.
SECTION2 - INTRODUCTION
The SGS - Thomson SS7 SignallingLink Control-
ler (MK50H27) is a VLSI semiconductor device
which provides a complete level 2 data communi-
cation control conforming to the CCITT, ANSI,
BELLCORE, and AT&T versions of SS7, as well
as options to allow conformance to TTC JT-Q703
(JapaneseSS7). This includes signal unit format-
ting, transparency (so-called ”bit-stuffing”), error
recovery by two types of
monitoring, sequence number control, link status
control,and fill in signal unit generation.
One of the outstandingfeatures of the MK50H27
is its buffer management which includes on-chip
DMA. This feature allows users to handle multi-
ple MSU’s of receive and transmit data at a time.
(A conventionaldata link control chip plus a sepa-
rate DMA chip would handledata for only a single
block at a time.) The MK50H27 will move multiple
blocks of receive and transmit data directly into
retransmission, error
September 1997
DIP48
PLCC 52
1/56