參數(shù)資料
型號： MK50H28N25
廠商： 意法半導(dǎo)體
英文描述： MULTI LOGICAL LINK FRAME RELAY CONTROLLER
中文描述： 多邏輯鏈路幀中繼控制器
文件頁數(shù)： 1/64頁
文件大?。?/td> 429K
代理商： MK50H28N25
MK50H28
MULTI LOGICAL LINK
FRAME RELAY CONTROLLER
SECTION1 - FEATURES
Based on ITU Q.933 Annex A and T1.617 An-
nex D Standards for Frame Relay Service and
Additional Pocedures for Permanent Virtual
Circuits(PVCs).
Optional Transparent Mode (no LMI Protocol
Processing - all frame data received).
Local Management Link Protocol with optional
Bi-directional messageprocessing.
Detects and indicates service-affecting errors
in the timing or content of events.
Programmable
Timers/Counters:
nT2/T392, nN1/N391, nN2/N392, nN3/N393
and dN1for the LMI/LIVchannel.
Provides Error Counters for the LMI channel
and Congestion Statistics for all the active
channels.
LMI/LIV Frames can be transmitted/received
on DLCI0 or 1023.
Supportsreception of up to 4 octets of address
field with a maximum of 8192 active channels
or DLCIs(Data Link ConnectionIdentifiers)
Priority DLCI scheme for channels requiring
higher rate of service.
BufferManagementincludes:
- InitializationBlock
- AddressLook Up Table
- ContextTable
- SeparateReceive and Transmit Rings of vari-
able size for each active channel
On chip DMA control with programmable burst
length.
Handles all HDLC frame formatting:
- Zerobit insertionand deletion
- FCS (CRC) generationand detection
- Framedelimiting with flags
Programmable minimum frame spacing on
transmission (1-62 flags between frames).
SelectableFCS (CRC) of 16 or 32 bits.
Testing Facilities: Internal Loopback, Silent
Loopback,Clockless Loopback,and Self Test.
Systemclock rates up to 25 MHz.
CMOS process; Fully compatible with both 8
and 16 bit systems; All inputs and outputs are
TTL compatible.
Programmablefor full or half duplexoperation.
nT1/T391,
Pin-for-pin compatible and architecturally the
same as the MK50H25 (X.25/LAPD) and
MK50H27 (CCS#7).
SECTION2 - DESCRIPTION
The STMicroelectronics MK50H28 Multi-Logical
Link Communications Controller is a CMOS VLSI
device which provides link level data communica-
tions control for Frame Relay Applicationson Per-
manent Virtual Circuits (PVCs).
will perform frame formating including: frame de-
limiting with flags, transparency (so-called ”bit-
stuffing”), plus FCS (CRC) generation and detec-
tion. It also supports Local ManagementInterface
(LMI)protocol with the ”O(jiān)ptionalBidirectional Pro-
cedures” (Annex D, T1.617 - 1991 and T1.617a-
1994).
The MK50H28
One of the outstandingfeatures of the MK50H28
is its buffer management which includes on-chip
dual channel DMA. This feature allows users to
receive and transmit multiple data frames at a
time. (A conventional serial communications con-
trol chip plus a separate DMA chip would handle
data for only a single block at a time.)
The
1/64
March 2000
DIP48
PLCC52
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MK50H28PLCC52 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER
MK50H28Q25 制造商:STMicroelectronics 功能描述:FRAME RELAY CTRL - Rail/Tube
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MK50N512CLL100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK50N512CLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
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