參數(shù)資料
型號： MK50DX256ZCMB10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
封裝： 8 X 8 MM, MAPBGA-81
文件頁數(shù)： 62/78頁
文件大?。?/td> 1068K
代理商： MK50DX256ZCMB10
6.8.6 I2C switching specifications
6.8.7 UART switching specifications
6.8.8 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 49. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
2 x tSYS
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
5 x tSYS
—
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
65
相關PDF資料
PDF描述
MK50DX256ZCLK10 FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
MK51DX256ZCLK10R 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
MK51DX256ZCMB10R 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
MK51DX256ZCLK10 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
MK51DX256ZCMB10 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
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