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參數(shù)資料
| 型號： | MK50DX256ZCMB10 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81 |
| 封裝： | 8 X 8 MM, MAPBGA-81 |
| 文件頁數(shù)： | 17/78頁 |
| 文件大?。?/td> | 1068K |
| 代理商： | MK50DX256ZCMB10 |
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Board type
Symbol
Description
81 MAPBGA
80 LQFP
Unit
Notes
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
TBD
°C/W
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
have CL=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
24
Preliminary
Freescale Semiconductor, Inc.
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