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| 型號(hào)： | MK50DX256ZCLL10 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, LQFP-100 |
| 文件頁(yè)數(shù)： | 37/73頁(yè) |
| 文件大?。?/td> | 991K |
| 代理商： | MK50DX256ZCLL10 |
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Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
Min.
Typ.2
Max.
Unit
Notes
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 × ENOB + 1.76
dB
THD
Total harmonic
distortion
16 bit differential mode
Avg=32
16 bit single-ended mode
Avg=32
—
–94
TBD
dB
SFDR
Spurious free
dynamic range
16 bit differential mode
Avg=32
16 bit single-ended mode
Avg=32
TBD
95
TBD
—
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
—
TBD
—
mV/°C
VTEMP25
Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. Input data is 1 kHz sine wave.
Figure TBD
Figure 13. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
Figure TBD
Figure 14. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
42
Preliminary
Freescale Semiconductor, Inc.
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