參數(shù)資料
型號: MK50DX256ZCLL10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 29/73頁
文件大?。?/td> 991K
代理商: MK50DX256ZCLL10
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
50
MHz
FB1
Clock period
20
ns
FB2
Address, data, and control output valid
11.5
ns
FB3
Address, data, and control output hold
0.5
ns
FB4
Data and FB_TA input setup
8.5
ns
FB5
Data and FB_TA input hold
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
35
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