參數(shù)資料
型號(hào): MK3720DLF
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 54 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁數(shù): 5/6頁
文件大小: 112K
代理商: MK3720DLF
27 MHZ AND 54 MHZ 3.3 VOLT VCXO
MDS 3720 I
5
Revision 061705
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
MK3720
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature 0 to +70
°C, unless stated otherwise
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Original MK3720S and MK3720A provided +100 ppm crystal pullability.
Note 3: Original MK3720S and MK3720A provided 100 and 170 ppm/V respectively.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.45
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
VDD-0.4
V
Operating Supply Current
IDD
No load
13
mA
Short Circuit Current
IOS
±50
mA
VIN, VCXO Control Voltage
VIA
03.3
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Crystal Pullability
FP
0V< VIN < 3.3V, Note 1
+ 115
ppm
VCXO Gain
VIN = VDD/2 +1 V, Note 1
120
ppm/V
Output Rise Time
tOR
0.8 to 2.0 V, CL=15 pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, CL=15 pF
1.5
ns
Output Clock Duty Cycle
tD
Measured at 1.4 V, CL=15 pF
45
50
55
%
Maximum Output Jitter,
short term
tJ
CL=15 pF, 13.5M CLK
80
ps
CL=15 pF, 27M and 54M CLK
150
ps
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