- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45329 > MK30N512VMD100 (FREESCALE SEMICONDUCTOR INC) 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 PDF資料下載
參數(shù)資料
| 型號(hào)： | MK30N512VMD100 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁(yè)數(shù)： | 40/72頁(yè) |
| 文件大?。?/td> | 1847K |
| 代理商： | MK30N512VMD100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)
Table 27. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
ENOB
Effective number
of bits
Gain=1, Average=4
Gain=1, Average=8
Gain=64, Average=4
Gain=64, Average=8
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32
TBD
12.3
12.7
8.4
8.7
13.3
13.1
12.5
11.8
11.1
10.2
9.3
—
bits
16-bit
differential
mode,
fin=500Hz
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function if input common mode voltage (VCM) and the PGA gain.
3. This is the input leakage current of the module in addition to the PAD leakage current.
4. Gain = 2PGAG
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 28. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
20
mV
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
45
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK30X128VMD100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| MK30X128VLQ100R | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
| MK30X256VMD100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| MK30X256VMD100R | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| MK30N512VLQ100R | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK30N512VML100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K30 Sub-Family Data Sheet |
| MK30R1F | 制造商:Ohmite Mfg Co 功能描述: |
| MK30X128VLQ100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K30 Sub-Family Data Sheet |
| MK30X128VMD100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K30 Sub-Family Data Sheet |
| MK30X256VLQ100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K30 Sub-Family Data Sheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。