參數(shù)資料
型號(hào): MK30DX256ZVMD10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 51/72頁
文件大?。?/td> 1013K
代理商: MK30DX256ZVMD10
6.8.3 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
25
MHz
DS1
DSPI_SCK output cycle time
2 x tBUS
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2)
2
ns
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2)
2
ns
DS5
DSPI_SCK to DSPI_SOUT valid
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
2
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3
DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data
Data
Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 23. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
12.5
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
55
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