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參數(shù)資料
| 型號： | MK20N512VML100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA104 |
| 封裝： | 8 X 8 MM, MAPBGA-104 |
| 文件頁數(shù)： | 49/61頁 |
| 文件大?。?/td> | 888K |
| 代理商： | MK20N512VML100R |
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S15
S13
S15
S17
S18
S15
S16
S14
S16
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 23. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 General Switching Specifications
These general purpose specifications apply to all signals configured for GPIO, SCI,
FlexCAN, CMT, and I2C signals.
Table 43. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled) — Synchronous path
1.5
—
Bus clock
cycles
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled, analog filter enabled) — Asynchronous path
100
—
ns
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled, analog filter disabled) — Asynchronous path
16
—
ns
External reset pulse width (digital glitch filter disabled)
TBD
—
Mode select (EZP_CS) hold time after reset deasser‐
tion
2
—
Bus clock
cycles
Port rise and fall time (high drive strength)
Slew disabled
Slew enabled
—
12
36
ns
Port rise and fall time (low drive strength)
Slew disabled
Slew enabled
—
32
36
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
53
Preliminary
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| MK20N512VMB100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81 |
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