參數(shù)資料
型號： MK20N512VML100R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PBGA104
封裝： 8 X 8 MM, MAPBGA-104
文件頁數(shù)： 44/61頁
文件大?。?/td> 888K
代理商： MK20N512VML100R
6.8.5 DSPI Switching Specifications (High-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master Mode DSPI Timing (High-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
DS1
DSPI_SCK output cycle time
2 x tBCLK
—
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) 2
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) 2
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
DS3
DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data
Data
Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 19. DSPI Classic SPI Timing — Master Mode
Table 39. Slave Mode DSPI Timing (High-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
12.5
MHz
DS9
DSPI_SCK input cycle time
4 x tBCLK
—
ns
DS10
DSPI_SCK input high/low time
(tSCK/2) 2
(tSCK/2 + 2
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
TBD
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
49
Preliminary
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