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參數(shù)資料
| 型號： | MK2069-02GITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 210K |
| 代理商： | MK2069-02GITR |
MK2069-02
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
9
MK2069-02
REV G 050203
Example Loop Filter Component Values
Notes:
1) The above examples illustrate the ability to adjust the VCXO PLL loop bandwidth by changing the PV Divider setting
only. Settings of the Translator PLL do not affect the VCXO PLL loop bandwidth, so a TCLK output frequency of 77.76
MHz or 155.52 MHz could be present, for example, with any of the above configurations. A VCXO gain (Kvco) of 4200
MHz/V was used for all bandwidth calculations.
2) The top group of settings use a minimal sized loop filter capacitor CS which minimizes cost and board space.
3) The middle group of settings use a larger sized loop filter capacitor CP allowing a lower PV Divider setting for similar
bandwidth and damping performance. This provides a higher phase detector frequency (equal to the RCLK frequency,
as shown) which is needed in applications subject to higher frequency reference clock jitter to avoid jitter aliasing. Note
that a higher phase detector frequency reduces jitter tolerance as well.
4) The bottom group of settings also use a larger sized loop filter capacitor CS, but an increased PV Divider setting to
achieve higher damping factors. A damping factor of 4 or higher is required to assure a passband ripple of <0.2 dB
which is required to comply with the Bellcore GR-1244-CORE wander transfer limit. The value of CP also must not be
excessive.
5) This setting would be a good choice for many 19.44 MHz jitter attenuation applications. It could be used, for example,
when following a system synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum
3 compliance. A 155.52 MHz TCLK output generated with this VCXO PLL configuration will be OC-3 and OC-12 timing
jitter compliant. The 80 Hz bandwidth is high enough to allow the MT9045 jitter transfer characteristics to dominate,
yet low enough to provide good jitter attenuation. The passband peak occurs past the MT9045 frequency roll-off point,
further protecting against excessive wander transfer gain. This higher loop bandwidth also provides improved stability
of the VCXO circuit.
Input
(ICLK)
Frequency
Xtal
Freq
(MHz)
VCLK
(MHz)
RCLK
(MHz)
PV
Div
FV
Div
SV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Notes
19.44 MHz
19.44
0.008 2430
11
1 M
Ω 560 kΩ 0.1 μF1 nF
24 Hz
1.3
1 dB at 5Hz
2
19.44 MHz
19.44
19.44 0.0162 1200
11
1 M
Ω 560 kΩ 0.1 μF1 nF
48 Hz
1.9
0.5 dB at 7Hz
2
19.44 MHz
19.44
19.44 0.0324 600
11
1 M
Ω 560 kΩ 0.1 μF1 nF 110 Hz
2.6
0.3 dB at 10Hz
2
19.44 MHz
19.44
19.44 0.6075
32
11
2 M
Ω 22 kΩ
1
μF
22 nF
38 Hz
1
1.5 dB at 11Hz
3
19.44 MHz
19.44
1.215
16
11
2 M
Ω 22 kΩ
1
μF
22 nF
70 Hz
1.4
0.75dB at 13Hz
3
19.44 MHz
19.44
9.72
2
11
2 M
Ω 22 kΩ
1
μF
22 nF 550 Hz
4
0.15dB at 30Hz
3
19.44 MHz
19.44
19.44 0.0648 300
11
2 M
Ω 168 kΩ 1 μF 4.7 nF 30 Hz
2.5
0.3dB at 3Hz
4
19.44 MHz
19.44
0.162
120
11
2 M
Ω 168 kΩ 1 μF 4.7 nF 80 Hz
4
0.15dB at 5Hz
4,5
19.44 MHz
19.44
0.249
78
11
2 M
Ω 168 kΩ 1 μF 4.7 nF 140 Hz
5
0.15dB at 10Hz
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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