參數(shù)資料
型號(hào)： MK2069-02GITR
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 17/21頁(yè)
文件大小： 210K
代理商： MK2069-02GITR
MK2069-02
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
5
MK2069-02
REV G 050203
Application Information
The MK2069-02 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
Where:
f(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
the pullable range of the crystal. This is guaranteed to be
+/-115 ppm minimum. This tracking range in ppm also
applies to the input clock and all clock outputs if the device
is to remain frequency locked to the input, which is required
for normal operation.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 1 to 8
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2 or 16
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-02 Loop Response and JItter
Attenuation Characteristics
The MK2069-02 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-02 passive
components and other device setting as explained in the
following section.
f(VCLK)
FV Divider
f(ICLK)
×
=
f(VCLK)
fVCXO
()
SV Divider
-----------------------
=
f(TCLK)
FT Divider
f(VCLK)
×
=
f(TCLK)
f(VC0)
ST Divider
-----------------------
=
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