參數(shù)資料
型號(hào)： MK2069-02GILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 347K
代理商： MK2069-02GILF
VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
11
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
Power Supply Considerations
As with any integrated clock device, the MK2069-02
has a special of set power supply requirements:
The feed from the system power supply must be
filtered for noise that can cause output clock jitter.
Power supply noise sources include the system
switching power supply or other system components.
The noise can interfere with device PLL components
such as the VCO or phase detector.
Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device
circuit block from interfering with another circuit
block.
Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may
result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply
Connection, below. The main features of this circuit are
as follows:
Only one connection is made to the PCB power
plane.
The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass ‘pi’ filter
that remove noise from the power supply as well as
clock noise back toward the supply. The bulk
capacitor should be a tantalum type, 1
F minimum.
The other capacitors should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin
as possible. There should be no via’s between the
decoupling capacitor and the supply pin.
Recommended Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to
reduce EMI. To series terminate a 50
trace, which is a
commonly used PCB trace impedance, place a 33
resistor in series with the clock line as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20
.
Quartz Crystal
The MK2069-02 operates by phase-locking the VCXO
circuit to the input signal at the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters must be used, and the
layout guidelines discussed in the following section
must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the load capacitors
connected to it. The MK2069-02 incorporates variable
load capacitors on-chip which “pull” or change the
frequency of the crystal. The crystals specified for use
with the MK2069-02 are designed to have zero
frequency error when the total of on-chip + stray
C onnection Via to
3.3V Pow er Plane
F errite
Chip
0.
1
F
BU
L
K
1
n
F
VD D
Pin
0.
0
1
F
VD D
Pin
0.01
F
VD D
Pin
0.
0
1
F
VD D
Pin
0.
0
1
F
相關(guān)PDF資料
PDF描述
MK2069-02GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
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