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參數(shù)資料
| 型號： | MK2058-01SITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 254K |
| 代理商： | MK2058-01SITR |
MK2058-01
COMMUNICATIONS CLOCK JITTER ATTENUATOR
VCXO AND SYNTHESIZER
IDT COMMUNICATIONS CLOCK JITTER ATTENUATOR
2
MK2058-01
REV G 051310
Pin Assignment
20-pin 300 mil SOIC
Output Clock Selection Table
Note: For SEL input pin programming:
0 = GND, 1 = VDD, M = Floating
Pin Descriptions
16
1
15
2
14
X1
X2
3
13
VDD
4
12
VDD
GND
5
11
VDD
6
ISEL
7
VIN
8
GND
ICLK1
ICLK2
SEL0
GND
CLK
GND
NC
9
10
CHGP
SEL1
ISET
SEL2
20
19
18
17
SEL2 SEL1 SEL0
Input / Output
Range
Crystal
Frequency
0
3.3 to 8.7 kHz
3072 x ICLK
0
1
0.64 to 1.68 MHz
16 x ICLK
0
1
0
1 to 2.7 MHz
10 x ICLK
0
1
1.7 to 4.5 MHz
6 x ICLK
M
0
5 to 13 kHz
2048 x ICLK
M
0
1
6 to 15.75 kHz
1716 x ICLK
M
1
0
26 to 70 kHz
384 x ICLK
M
1
70 to 210 kHz
128 x ICLK
1
0
2.5 to 6.75 MHz
4 x ICLK
1
0
1
3.4 to 9 MHz
3 x ICLK
1
0
5 to 13.5 MHz
2 x ICLK
1
10 to 27 MHz
1 x ICLK
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
—
Crystal Input. Connect this pin to the specified crystal.
2
VDD
Power
Power Supply. Connect to +3.3 V.
3
VDD
Power
Power Supply. Connect to +3.3 V.
4
VDD
Power
Power Supply. Connect to +3.3 V.
5
VIN
Input
VCXO Control Voltage Input. Connect this pin to CHGP pin and the external
loop filter as shown in this data sheet.
6
GND
Power
Connect to ground.
7
GND
Power
Connect to ground.
8
GND
Power
Connect to ground.
9
CHGP
Output
Charge Pump Output. Connect this pin to the external loop filter and to pin
VIN.
10
ISET
—
Charge pump current setting node, connection for setting resistor.
11
SEL2
Input
Output Frequency Selection Pin 2. Determines output frequency as per table
above. Internally biased to VDD/2.
12
SEL1
Input
Output Frequency Selection Pin 1. Determines output frequency as per table
above. Internal pull-up resistor.
13
NC
Input
No Internal Connection.
14
CLK
Output
Clock Output.
15
SEL0
Input
Output Frequency Selection Pin 0. Determines output frequency as per table
above. Internal pull-up resistor.
16
ICLK2
Input
Input Clock Connection 2. Connect an input reference clock to this pin. If
unused, connect to ground.
17
ICLK1
Input
Input Clock Connection 1. Connect an input reference clock to this pin. If
unused, connect to ground.
18
ISEL
Input
Input Selection. Used to select which reference input clock is active. Low input
level selects ICLK1, high input level selects ICLK2. Internal pull-up resistor.
19
GND
Power
Connect to ground.
20
X2
—
Crystal Output. Connect this pin to the specified crystal.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| MK2059-01 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK2059-01SILF | 功能描述:時鐘合成器/抖動清除器 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2059-01SILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2059-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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