- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄95954 > MK2049-34SAILF (INTEGRATED DEVICE TECHNOLOGY INC) 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | MK2049-34SAILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOIC-20 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 213K |
| 代理商： | MK2049-34SAILF |
MK2049-34A
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
VCXO AND SYNTHESIZER
IDT / 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
3
MK2049-34A REV E 051310
Output Decoding Table - External Mode (MHz)
Output Decoding Table - Loop Timing Mode (MHz)
Output Decoding Table - Buffer Mode (MHz)
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-34A has three operating modes: External, Loop Timing, and Buffer. Although each mode uses an input clock
to generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies.
The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable. In
the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the 8 kHz ICLK; refer to Figure
1 on page 4 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1 and E1 inputs, the
CLK/2 output will be the same as the input frequency, with CLK at twice the input frequency.
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8k
Crystal
Used (MHz)
N
8 kHz
0000
1.544
3.088
8 kHz
12.352
1544
8 kHz
0001
2.048
4.096
8 kHz
12.288
1536
8 kHz
0010
22.368
44.736
8 kHz
11.184
1398
8 kHz
0011
17.184
34.368
8 kHz
11.456
1432
8 kHz
0100
19.44
38.88
8 kHz
9.72
1215
8 kHz
0101
16.384
32.768
8 kHz
8.192
1024
8 kHz
0110
17.664
35.328
8 kHz
17.664
2208
8 kHz
0111
18.688
37.376
8 kHz
9.344
1168
8 kHz
1010
7.68
15.36
8 kHz
15.36
1920
8 kHz
1011
10.752
21.504
8 kHz
10.752
1344
8 kHz
1100
10.24
20.48
8 kHz
10.24
1280
8 kHz
1101
38.88
77.76
8 kHz
9.72
1215
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8k
Crystal
N
1.544
1000
1.544
3.088
N/A
12.352
24
2.048
1001
2.048
4.096
N/A
12.288
18
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8k
Crystal
N
19 - 36
1110
ICLK/2
ICLK
N/A
ICLK/2
3
10 - 18
1111
2*ICLK
4*ICLK
N/A
ICLK
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SAI | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-34SI | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-34SITR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2704S | 36.864 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| MK2705S | 24.576 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SAILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAITR | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。