- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45328 > MK2049-11SITRLF (INTEGRATED DEVICE TECHNOLOGY INC) 56 MHz, OTHER CLOCK GENERATOR, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | MK2049-11SITRLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MK2049-11SITRLF |
Communications Clock PLL
MDS 2049-11 C
6
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Loop Filter Capacitor Type
Loop filter capacitors C1 and C2 should be film type.
This includes the PPS polymer film type made by
Panasonic, or metal poly types made by MuRata or
Cornell Dublier.
The Panasonic ECP-U and ECH-U series capacitors
are typically used on the ICS MK20xx demo boards
and are found to work well. These devices are
available from Digi-Key.
Other acceptable capacitor types include those with
C0G or NP0 dielectric.
Avoid high-K dielectrics like Z5U and X7R (these are
acceptable for the decoupling capacitors, however).
The loop capacitors must have a high dielectric
resistance to avoid leakage-induced phase noise. For
this reason, DO NOT use any type of polarized or
electrolytic capacitors. Microphonics (mechanical
board vibration) will also induce output phase noise.
High-K dielectrics like Z5U and X7R have piezoelectric
properties that convert mechanical vibration into
voltage noise that interferes with VCXO operation.
For additional questions, please contact your ICS
Sales FAE or contact ICS MicroClock applications at
(408) 297-1201.
Power Supply Considerations
As with any integrated clock device, the MK2049-11
has a special set of power supply requirements:
The feed from the system power supply must be
filtered for noise that can cause output clock jitter.
Power supply noise sources include the system
switching power supply or other system components.
The noise can interfere with various internal device
circuit blocks such as the VCO or phase detector.
Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device
circuit block from interfering with another circuit
block.
Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may
result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply
Connection, below. The main features of this circuit are
as follows:
Only one connection is made to the PCB power
plane.
The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass ‘pi’ filter
that remove noise from the power supply as well as
clock noise back toward the supply. The bulk
FS3:1
Input
Clock
(ICLK)
External
Crystal
Freq
(MHz)
VCXO PLL
‘N’
(feedback
divider)
Value
RZ
C1
C2
Approximate
Loop
Bandwidth
(-3dB point)
Approximate
Damping
Factor
000
8 kHz
12.352
1544
2.7 M
0.1
F
330 pF
40 Hz
4
001
8 kHz
11.456
1432
2.7 M
0.1
F
330 pF
40 Hz
4
010
8 kHz
12.96
1620
2.7 M
0.1
F
330 pF
40 Hz
4
011
8 kHz
12.96
1620
2.7 M
0.1
F
330 pF
40 Hz
4
100 1.544 MHz
12.352
8
47 k
0.1
F
4.7 nF
180 Hz
1
Filter Option for Above Mode
22 k
1
F
47 nF
90 Hz
1.4
101
34.368
MHz
11.456
2
24 k
0.1
F
4.7 nF
400 Hz
1
Filter Option for Above Mode
11 k
1
F
47 nF
180 Hz
1.4
110
8 kHz
10.24
1280
2.7 M
0.1
F
330 pF
40 Hz
4
111
10-14 MHz
ICLK
6
43 k
0.1
F
4.7 nF
220 Hz
1
Filter Option for Above Mode
18 k
1
F
47 nF
100 Hz
1.4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASI | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2069-01GILFTR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-01GITR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-01GI | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設(shè)備封裝:* 包裝:* |
| MK2049-34SAILF | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。