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參數(shù)資料
| 型號： | MK1575-01GI |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 217K |
| 代理商： | MK1575-01GI |
CLOCK RECOVERY PLL
MDS 1575-01 L
4
Revision 070605
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK1575-01
Functional Description
The MK1575-01 is a PLL (phase-locked loop) based
clock generator that generates output clocks
synchronized to an input reference clock. The device
can be used in the standard configuration as described
on page 1, or optionally can use an external divider in
the clock feedback path to produce other frequency
multiplication factors.
External components are used to control the PLL loop
response. The use of external loop components
enables a lower PLL loop bandwidth which is needed
when accepting low frequency input clocks such as
those listed in the tables on page 1.
PLL Clock Feedback Options
FCLK to FBIN
This is the standard configuration that is used for the
pre-configured input / output frequency combinations
listed on page 1. By including an external divider in the
feedback path (“FB Divider” in the Block Diagram of
page 3) the output clock frequency can be increased.
Refer to the Output Frequency Calculation table below.
CLK1 to FBIN
When no external feedback divider is used, this option
configures the device as a zero-delay buffer and the
frequency of CLK1 is the same as the input reference
clock. Including an external divider in the feedback path
will increase the output clock frequency. Refer to the
Output Frequency Calculation table below.
CLK2 to FBIN
Like the above configuration, this option configures the
device as a zero-delay buffer when no external
feedback divider is used, and the frequency of CLK2 is
the same as the input reference clock. Including an
external divider in the feedback path will increase the
output clock frequency. Refer to the Output Frequency
Calculation table below.
Frequency and Bandwith Calculations
Notes:
1) FB = 1 when no feedback divider is used.
2) Refer to the Detail Mode Selection Table on page 3 for possible divider combinations.
3) The VCO frequency needs to be considered in all applications (see table below).
4) The external loop filter also needs to be considered.
5) Minimum VCO frequency = 96 MHz.
6) Maximum VCO frequency = 320 MHz.
7) To minimize output jitter, use the highest possible VCO frequency allowed by the application.
Feedback
Path
Option
Output Clock Frequency
CLK1
CLK2
FCLK
VCO
Frequency
“N” Factor
FCLK to
FBIN
CLK1 to
FBIN
CLK2 to
FBIN
f
IN
FB
×
FCLK
×
f
IN
FB
×
FCLK
CLK2
----------------
×
f
IN
FB
×
f
IN
FB
×
FCLK
2
×
f
IN
FB
×
VS
×
VS
FCLK
×
FB
×
f
IN
FB
×
f
IN
FB
×
CLK2
----------------------
f
IN
FB
×
FCLK
---------------------VS
FB
×
f
IN
FB
×
CLK2
×
f
IN
FB
×
f
IN
FB
×
CLK2
FCLK
----------------
×
f
IN
FB
×
CLK2
2
×
VS
×
VS
CLK2
×
FB
×
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PDF描述 |
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| MK1575-01G | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1575-01GITR | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1707SLFTR | 1707 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MK1707STR | PLL BASED CLOCK DRIVER, PDSO8 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GLF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GLFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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