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參數(shù)資料
| 型號： | MK1575-01GI |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 217K |
| 代理商： | MK1575-01GI |
CLOCK RECOVERY PLL
MDS 1575-01 L
8
Revision 070605
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK1575-01
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin
as possible. There should be no vias between the
decoupling capacitor and the supply pin.
Optimum Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to
reduce EMI. To series terminate a 50
trace, which is a
commonly used PCB trace impedance, place a 33
resistor in series with the clock line as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20
.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following printed circuit board layout
recommendations should be observed.
1) Each 0.01F power supply decoupling capacitor
should be mounted as close to the VDD pin as
possible. The PCB trace to VDD pin should be kept as
short as possible, as should the PCB trace to the
ground via. Distance of the ferrite chip and bulk
decoupling from the device is less critical.
2) The loop filter components (RZ, CS and CB) must
also be placed close to the CHGP and VIN pins. CB
should be closest to the device. Coupling of noise from
other system signal traces should be minimized by
keeping traces short and away from active signal
traces. Use of vias should be avoided.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
4) Because each input selection pin includes an
internal pull-up device, those inputs requiring a logic
high state (“1”) can be left unconnected. The pins
requiring a logic low state (“0”) can be grounded.
Loss of Reference Clock
If a loss occurs on the REFIN clock, the output
frequency will decrease at a rate of
where:
C = C1 + C2
VS = value of VS divider (from the table on page 3)
If the input is held low, the output will stop high or low,
or might toggle at several Hz.
Low Frequency Operation
The output frequency can be extended below 1.5 MHz
by adding a divider in the output path. In this
configuration, it is desirable to take the feedback signal
from CLK1 rather than the output of the divider.
However, if zero delay operation is required, the
feedback signal must come from the divider output.
MK1575-01 Typical VCO Transfer Curve
Connection Via to 3.3V
Power Plane
Ferrite
Chip
0.
1
F
BULK
1nF
VDDA
Pin
0.
01
F
VDDD
Pin
0.
01
F
10
df
dt
4250
C x VS
=
Hz/s
0
100
200
300
400
500
600
700
00.5
11.5
22.5
33.5
Vin
MH
z
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| MK1575-01G | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GLF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GLFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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