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參數(shù)資料
| 型號： | MK1493-14GLF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.173 INCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 167K |
| 代理商： | MK1493-14GLF |
SPREAD SPECTRUM CLOCK GENERATOR
MDS 1493-14 A
12
Revision 082205
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK1493-14
Notes
1) The typical frequency is not specified since this is a spread clock.
2) Measured at 10 s.
3) This spread range and rate result in a cycle- to -cycle jitter 0f 0.1 ps.
4) Longest period including jitter and spread minus shortest period including jitter and spread equals 301 ps.
5) longest period including jitter and spread minus shortest period including jitter and spread equals 352 ps.
6) Longest period including jitter and spread-Shortest period including jitter and spread equals 403.
7) When the output is transitioning between logic 0 and logic 1 or logic 1 and logic 0, the outputs shall monotonically
transition between VOL and VOH, VOH and VOL respectively.
8) Calculated as 2*(TR-TF)/(TR+TF).
9) Measured across RT( RT is termination, 50 ohm load).
10) Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions.
11) Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions.
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