參數(shù)資料
型號(hào): MK10DN512ZVMB10R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
封裝: 8 X 8 MM, MAPBGA-81
文件頁(yè)數(shù): 52/69頁(yè)
文件大小: 981K
代理商: MK10DN512ZVMB10R
6.8.6 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 42. SDHC switching specifications
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
tWL
Clock low time
7
ns
tWH
Clock high time
7
ns
tTLH
Clock rise time
3
ns
tTHL
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
tTHL
SDHC input setup time
5
ns
tTHL
SDHC input hold time
0
ns
SD2
SD3
SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 25. SDHC timing
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
56
Preliminary
Freescale Semiconductor, Inc.
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