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參數資料
| 型號： | MJL16218 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | POWER TRANSISTOR 15 AMPERES 1500 VOLTS - VCES 170 WATTS |
| 中文描述： | 15 A, 650 V, NPN, Si, POWER TRANSISTOR, TO-3PBL |
| 封裝： | TO-3PBL, 3 PIN |
| 文件頁數： | 6/8頁 |
| 文件大小： | 157K |
| 代理商： | MJL16218 |
6
Motorola Bipolar Power Transistor Device Data
DYNAMIC DESATURATION
The SCANSWITCH series of bipolar power transistors are
specifically designed to meet the unique requirements of hor-
izontal deflection circuits in computer monitor applications.
Historically, deflection transistor design was focused on mini-
mizing collector current fall time. While fall time is a valid
figure of merit, a more important indicator of circuit perfor-
mance as scan rates are increased is a new characteristic,
“dynamic desaturation.” In order to assure a linear collector
current ramp, the output transistor must remain in hard satu-
ration during storage time and exhibit a rapid turn–off transi-
tion. A sluggish transition results in serious consequences.
As the saturation voltage of the output transistor increases,
the voltage across the yoke drops. Roll off in the collector
current ramp results in improper beam deflection and distor-
tion of the image at the right edge of the screen. Design
changes have been made in the structure of the SCAN-
SWITCH series of devices which minimize the dynamic
desaturation interval. Dynamic desaturation has been
defined in terms of the time required for the VCE to rise from
1.0 to 5.0 volts (Figures 9 and 10) and typical performance at
optimized drive conditions has been specified. Optimization
of device structure results in a linear collector current ramp,
excellent turn–off switching performance, and significantly
lower overall power dissipation.
U2
MC7812
G
N
D
VI
VO
+
+
+
+
+24 V
C1
100
μ
F
C2
10
μ
F
C3
10
μ
F
R7
2.7 k
R8
9.1 k
R9
470
R10
47
C5
0.1
C4
0.005
R2
R510
R3
250
R6
1 k
R12
470
1 W
D1
MUR110
T1
LB
R4
22
Q4
DUT
VCE
CY
LY
C6
100
μ
F
R5
1 k
(IC)
(IB)
Q5
MJ11016
Q2
MJ11016
Q3
MJE
15031
R11
470
1 W
100 V
D2
MUR460
U1
MC1391P
%
OSC
VCC
OUT
GND
7
6
8
1
2
(DC)
BS170
Q1
SYNC
Table 2. High Resolution Deflection Application Simulator
R1
1 k
6.2 V
T1:Ferroxcube Pot Core #1811 P3C8
Primary/Sec. Turns Ratio = 18:6
Gapped for LP = 30
μ
H
LB = 1.5
μ
H
CY = 0.01
μ
F
LY = 13
μ
H
V
I
Figure 11. Deflection Simulator Circuit Base
Drive Waveform
TIME (2
μ
s/DIV)
IB1 = 2.2 A
Figure 12. Definition of Dynamic
Desaturation Measurement
TIME (ns)
tds
DYNAMIC DESATURATION TIME
IS MEASURED FROM VCE = 1 V
TO VCE = 5 V
1
4
5
0
3
2
0
6
8
4
2
10
IB2 = 4.5 A
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