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參數(shù)資料
| 型號： | MJ80C32U-25:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 38/109頁 |
| 文件大小： | 10824K |
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282
7593L–AVR–09/12
AT90USB64/128
4 - NAKOUTI - NAK OUT Received Interrupt flag
Set by hardware when a NAK handshake has been sent in response of a OUT/PING request
from the host. This triggers an USB interrupt if NAKOUTE is sent.
Shall be cleared by software. Setting by software has no effect.
3 - RXSTPI - Received SETUP Interrupt flag
Set by hardware to signal that the current bank contains a new valid SETUP packet. An inter-
rupt (EPINTx) is triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an IN endpoint.
2 - RXOUTI / KILLBK - Received OUT Data Interrupt flag
Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
Kill Bank IN bit
Set this bit to kill the last written bank.
Cleared by hardware when the bank is killed. Clearing by software has no effect.
See page 271 for more details on the Abort.
1 - STALLEDI - STALLEDI Interrupt flag
Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been
detected in a OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
0 - TXINI - Transmitter Ready Interrupt flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
7 - FLERRE - Flow Error Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
6 - NAKINE - NAK IN Interrupt Enable bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
Bit
7
6
5
4
3
210
FLERRE
NAKINE
-
NAKOUTE
RXSTPE
RXOUTE
STALLEDE
TXINE
UEIENX
Read/write
R/W
R
R/W
Initial value
0
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