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參數(shù)資料
| 型號(hào)： | MIP7965-668F24M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 668 MHz, MICROPROCESSOR, CQFP208 |
| 封裝： | 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208 |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大?。?/td> | 310K |
| 代理商： | MIP7965-668F24M |
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7
SCD7965 Rev H 10/01/10
Aeroflex Plainview
ABSOLUTE MAXIMUM RATINGS 1
SYMBOL
RATING
RANGE
UNITS
VTERM
Terminal Voltage with respect to Vss
-0.5 2 to +3.9
V
Tc
Operating Temperature
I = Commercial
R = Commercial
Class H = Extended, Screened
-40 to +85
-55 to +110
C
TSTG
Storage Temperature
-55 to +125
C
IIN
DC Input Current
±20
mA
IOUT
DC Output Current 4
±20
mA
Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +3.95 Volts.
3. When VIN < 0V or VIN > VccIO.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 seconds.
RECOMMENDED OPERATING CONDITIONS
GRADE
CPU
SPEED
TEMP
(CASE)
Vss
VccInt
VccIO
VccP
VccJ
Commercial
(I)
750
MHz
-40°C to+85°C
0 V
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
668
MHz
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
Commercial
(R)
750
MHz
-55°C to
+110°C
0 V
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
668
MHz
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
Extended
Screened
(Class H)
668
MHz
-55°C to
+110°C
0 V
1.3 V ± 50 mV
3.3 V ± 150 mV
1.3 V ± 50 mV
3.3 V ± 150 mV
Notes
1. VccIO should not exceed VccInt by greater than 2.5 V during the power-up sequence.
2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the
RM79xx User Manual.
4. VccP must be connected to VccInt through a passive filter circuit. See RM79xx User Manual for recommended circuit. Not applicable
for the F17, F24 QFP and Interposer evaluation board devices which incorporates the filter components except for the 10F capacitor.
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