參數(shù)資料
型號(hào)： MIC74YQS TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 6/18頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16QSOP
標(biāo)準(zhǔn)包裝： 2,500
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 是
電源電壓： 2.7 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
其它名稱： MIC74YQSTR
MIC74YQSTR-ND
Micrel, Inc.
MIC74
October 2006
14
M9999-101006
Polled Mode
Input state changes on I/O’s configured as inputs will be
reflected in the status register regardless of the state of
the global interrupt enable bit (IE) and the individual
interrupt mask bits in INT_MASK. In a system utilizing
polling to monitor for input changes, the status register is
periodically read to check for input events. The act of
reading STATUS clears it in preparation for detecting
future events. The status bits corresponding to I/O’s
configured as outputs or corresponding to P[7:4] when in
fan mode will not be set by state changes on these pins.
It is always good practice, however, to mask the value
obtained when reading STATUS to eliminate any bits,
output or otherwise, that are not of immediate concern.
This will help avoid problems if software changes are
made in the future.
The flowchart shown in Figure 9a illustrates the steps
involved in initializing the MIC74 for polled operation.
The flowchart in Figure 10 illustrates the corresponding
polling routine. The process for writing output data is
straight-forward—simply write the desired bit pattern to
DATA. (Special precautions may be required when
changing output data in an interrupt driven system,
however. See the discussion below under “Writing to the
Data Register.”)
Interrupt Mode
Input state changes on I/Os configured as inputs will be
reflected in the status register regardless of the state of
the global interrupt enable bit (IE) and the individual
interrupt mask bits in INT_MASK. In a system utilizing
interrupts to detect input changes, one or more of the
bits in the interrupt mask register, INT_MASK, are set to
allow interrupts on/ALERT to be generated by input
events. The global interrupt enable bit, IE, in the device
configuration register must also be set to enable
interrupts.
The flowchart shown in Figure 9b illustrates the steps
involved in initializing the MIC74 for interrupt-driven
operation. The flowchart in Figure 11 illustrates the
corresponding interrupt service routine using the SMBus
ARA (alert response address). The corresponding timing
diagram is shown in Figure 7. The flowchart in Figure 12
illustrates the corresponding interrupt service routine
using polling to determine the interrupt source. Figure 8
illustrates the timing. Utilizing the ARA greatly speeds
identification of the interrupting slave device and lowers
latency, as only a single transaction on the bus is
necessary to identify the interrupt source.
Using either method, STATUS must be read to deter-
mine the exact source of the interrupt within the MIC74.
Read
STATUS
Is
Sx set
?
No
Yes
Polling the
MIC74
Service function x
Is
STATUS
h
?
Yes
No
Is
Sm set
?
No
Yes
Service function m
Is
Sn set
?
No
Yes
Service function n
Figure 10. Polling the MIC74
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