參數(shù)資料
型號： MIC74YQS TR
廠商： Micrel Inc
文件頁數(shù)： 14/18頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16QSOP
標準包裝： 2,500
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 是
電源電壓： 2.7 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 16-QSOP
包裝： 帶卷 (TR)
其它名稱： MIC74YQSTR
MIC74YQSTR-ND
Micrel, Inc.
MIC74
October 2006
5
M9999-101006
Register Descriptions
Device Configuration Register
DEV_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Always write as zero
FAN
IE
Power-On Default Value: 0000 0000b, 00h
Interrupts disabled
Not in Fan Mode
Command_byte addess: 0000 0000b, 00h
Type:
8-bits, read/write
Bit Name: IE
Function:
Global interrupt enable
Operation: 1 = enabled
0 = disabled
Bit Name: FAN
Function:
Selects Fan Mode
(P[7:4] vs. /FS[2:0], /SHDN)
Operation: 1 = Fan Mode
0 = I/O Mode
Bit Name: D[2] through D[6]
Function:
Reserved
Operation: Reserved—always write as zero
Data Direction Register
DIR
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Power-On Default Value: 0000 0000b, 00h
all Pn’s configured as inputs
Command_byte addess: 0000 0001b, 01h
Type:
8-bits, read/write
Bit Name: DIRn
Function:
Selects data direction, input or output, of Pn
Operation: 1 = output
0 = input
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The DIR register has no effect on
these I/O bits while in Fan Mode.
Output Configuration Register
OUT_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
Power-On Default Value: 0000 0000b, 00h
all outputs open-drain
Command_byte addess: 0000 0010b, 02h
Type:
8-bits, read/write
Bit Name: OUTn
Function:
Selects output driver configuration of Pn when
Pn is configured as an output.
Operation: 1 = push-pull
0 = open-drain
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The OUT_CFG register has no effect
on these I/O bits while in Fan Mode.
Status Register
STATUS
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
S7
S6
S5
S4
S3
S2
S1
S0
Power-On Default Value: 0000 0000b, 00h
no interrupts pending
Command_byte addess: 0000 0011b, 03h
Type:
8-bits, read only
Bit Name: Sn
Function:
Flag for Pn input-change event when Pn is
configured as an input; Sn is set when the
corresponding input changes state.
Operation: 1 = change occurred
0 = no change occurred
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
All status bits are cleared after any read
operation is performed on STATUS.
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