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參數(shù)資料
| 型號(hào)： | MIC2595R-2BM TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/29頁 |
| 文件大小： | 4205K |
| 描述： | IC CTRLR HOT SWAP NEG HV 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | -19 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2595R-2BMTR MIC2595R-2BMTR-ND |
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Micrel
MIC2589/MIC2595
December 2005
4
M9999-120505
(408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1
PWRGD1
(MIC25XX-1)
Active High
/PWRGD1
(MIC25XX-2)
Active Low
Power-Good Output 1: Asserted when the voltage on the DRAIN pin (V
DRAIN
) is within
V
PGTH
of VEE, indicating that the output voltage is within proper specifications. For
the MIC2589-1 and MIC2595-1, PWRGD1 will be high impedance when V
DRAIN
is
less than V
PGTH
, and will pull-down to V
DRAIN
when V
DRAIN
is greater than V
PGTH
. For
the MIC2589-2 and MIC2595-2, /PWRGD1 will pull-down to V
DRAIN
when V
DRAIN
is
less than V
PGTH
, and will be high-impedance when V
DRAIN
is greater than V
PGTH
.
2
PGTIMER
A capacitor connected from this pin to VEE sets the time interval between assertions
of PWRGD2 (or /PWRGD2) and PWRGD3 (or /PWRGD3) relative to PWRGD1 (or
/PWRGD1). See the Functional Description for further detail.
3
UV
(MIC2589
and
MIC2589R)
Undervoltage Threshold Input: When the voltage at the UV pin is less than the V
UVL
threshold, the GATE pin is immediately pulled low by an internal 100礎(chǔ) current pull-
down. The UV pin is also used to cycle the device off and on to reset the circuit
breaker. Taken together, the OV and UV pins form a window comparator that defines
the limits of V
EE
to deliver power to the load.
3
OFF
(MIC2595
and
MIC2595R)
Turn-Off Threshold: When the voltage at the OFF pin is less than the V
OFFL
threshold, the GATE pin is immediately pulled low by an internal 100礎(chǔ) current pull-
down. The OFF pin is also used to cycle the device off and on to reset the circuit
breaker. Taken together, the ON and OFF pins provide programmable hysteresis for
the MIC2595 to be enabled.
4
OV
(MIC2589
and
MIC2589R)
Overvoltage Threshold Input: When the voltage at the OV pin is greater than the
V
OVH
threshold, the GATE pin is immediately pulled low by an internal 100礎(chǔ) current
pull-down.
4
ON
(MIC2595
and
MIC2595R)
Turn-On Threshold: At initial system power-up or after the part has been shut off by
the OFF pin, the voltage on the ON pin must be above the V
ONH
threshold in order for
the MIC2595 to be enabled.
5
CFILTER
Current Limit Response Timer: A capacitor connected between this pin and VEE
provides filtering against nuisance tripping of the circuit breaker by setting a time
delay, t
FLT
, for which an overcurrent event must last prior to signaling a fault condition
and latching the output off. The minimum time for t
FLT
will be the time it takes for the
output (capacitance) to charge to VEE during start-up. This pin is held to VEE with a
3礎(chǔ) current pull-down when no current limit condition exists. See the Functional
Description for further details.
6
CNLD
No-Load Detect Timer: The absence of a load for the MIC2589/MIC2589R is defined
for any current load that is less than 20% of the full-scale current limit (i.e., 0.20 ?
I
LIM
). A capacitor between CNLD and VEE sets the filter delay, t
NLD
, for a load current
that is 80% (or greater) below the full-scale current limit before the circuit breaker is
tripped.
7
VEE
Negative Supply Voltage Input: Connect the negative, or low side, terminal of the
input power supply.
8
NC
No Internal Connection
9
SENSE
Circuit Breaker Sense Input: A resistor between this pin and VEE sets the current
limit trip point for the circuit. When the current limit threshold of IR = 50mV is
exceeded for t
FLT
, the circuit breaker is tripped and the GATE pin is immediately
pulled low by I
GATEOFF
. Toggling UV or OV will reset the circuit breaker. In order to
disable the circuit breaker (i.e., eliminate overcurrent V
SENSE
-V
EE
protection), connect
(short) the SENSE pin to VEE and also connect the CNLD pin to VEE to disable the
no-load detection feature.
10
GATE
Gate Drive Output: Connects to the Gate of an N-Channel MOSFET.
11
DRAIN
Drain Sense Input: Connects to the Drain of an N-Channel MOSFET.
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