參數(shù)資料
型號(hào): MIC2595R-2BM TR
廠商: Micrel Inc
文件頁數(shù): 18/29頁
文件大?。?/td> 4205K
描述: IC CTRLR HOT SWAP NEG HV 14-SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: -19 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 帶卷 (TR)
其它名稱: MIC2595R-2BMTR
MIC2595R-2BMTR-ND
Micrel
MIC2589/MIC2595
 
 
December 2005 
18
M9999-120505
 (408) 955-1690
 
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
CNLD
NLD
CNLD
NLD
I
C
V
t
 
where V
CNLD
  = 1.24V (typ); I
CNLD
  = 25礎(chǔ) (typ); and
C
NLD
 is an external capacitor connected from Pin 6 to
VEE. Once the voltage on CNLD reaches its no-load
threshold voltage, V
CNLD
, the loop times out and the
controller will shut down until it is reset manually
(MIC2589/MIC2595) or until it performs an auto-retry
operation (MIC2589R/MIC2595R). During start-up, the
no-load detection circuit begins to monitor the load
current and the CNLD pin starts ramping along with
the GATE output. In order to keep the output from
shutting down, t
NLD
  must be long enough to ensure
that the output MOSFET switches on to deliver the
required minimum load-detect current to the output
load before the no-load timer times out.
The Power-Good Output Signals
For
the
MIC2589/MIC2595-1
and
MIC2589R/MIC2595R-1, power-good output signal
PWRGD1 will be high impedance when V
DRAIN
 drops
below V
PGTH
, and will pull-down to the potential at the
DRAIN   when   V
DRAIN
   is   above   V
PGTH
.   For   the
MIC2589/95-2 and the MIC2589R/95R-2, power-good
output signal /PWRGD1 will pull down to the potential
of the DRAIN pin when V
DRAIN
 drops below V
PGTH
 and
will be high impedance when V
DRAIN
 is above V
PGTH
.
Hence, the -1 parts have an active-high PWRGDX
signal and the -2 parts have an active-low /PWRGDX
output. PWRGDX (or /PWRGDX) may be used as an
enable signal for one or more following DC/DC
converter modules or for other system uses as
desired. When used as an enable signal, the time
necessary for the PWRGD (or /PWRGD) signal to
pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3   (/PWRGD3)   follow   the   assertion   of
PWRGD1 (/PWRGD1) with a sequencing delay set by
an external capacitor (C
PG
) from the controllers
PGTIMER pin (Pin 2) to VEE. An expression for the
sequencing delay between PWRGD2 and PWRGD1
is given by:
PGTIMER
PG
)
THRESH(PG2
1
PGDLY2
I
C
V
t
?/DIV>
=

 
where VTHRESH(PG2) (= 0.63V, typically) is the
PWRGD2 threshold voltage for PGTIMER and I
PGTIMER
 
(= 45礎(chǔ), typically) is the internal PGTIMER charge
current. Similarly, an expression for the sequencing
delay between PWRGD3 and PWRGD2 is given by:
PGTIMER
PG
)
THRESH(PG2
)
THRESH(PG3
2
PGDLY3
I
C
V
V
t
?/DIV>

=

 
where V
THRESH(PG3)
  (1.15V,  typical)  is  the  PWRGD3 
threshold voltage for PGTIMER. Therefore, power-
good output signal PWRGD2 (/PWRGD2) will be
delayed after the assertion of PWRGD1 (/PWRGD1)
by:
t
PGDLY2-1
 (ms)   14 ?C
PG
(礔)
Power-good   output   signal   PWRGD3   (/PWRGD3)
follows the assertion of PWRGD2 by a delay:
t
PGDLY3-2
 (ms)   11.5 ?C
PG
(礔)
For example, for a 10礔 value for C
PG
, power-good
output signal PWRGD2 will be asserted 140ms after
PWRGD1. Power-good signal PWRGD3 will then be
asserted 115ms after
 PWRGD2 and 255ms after
 the
assertion of PWRGD1. The relationships between
V
DRAIN
, V
PGTH
, PWRGD1, PWRGD2, and PWRGD3
are shown in Figure 6.
Undervoltage/Overvoltage Detection (MIC2589 and
MIC2589R)
The MIC2589 and the MIC2589R have UV and OV
input pins that can be used to detect input supply rail
undervoltage
and
overvoltage
conditions.
Undervoltage   lockout   prevents   the   output   from
switching on until the supply input is stable and within
tolerance. In a similar fashion, overvoltage shutdown
prevents damage to sensitive circuit components
should the input voltage exceed normal operating
limits. Each of these pins is internally connected to
analog comparators with 20mV of hysteresis. When
the UV pin falls below its V
UVL
 threshold or the OV pin
is   above   its   V
OVH
   threshold,   the GATE   pin   is
immediately pulled low. The GATE pin will be held low
until the UV pin is above its V
UVH
 threshold and the OV
pin is below its V
OVL
 threshold. The circuits UV and
OV threshold voltage levels are programmed using
the resistor divider R1, R2, and R3 as shown in the
Typical Application circuit and the equations to set
the trip points are shown below. The circuits UV
threshold is set to V
UV
 = 37V and the OV threshold is
set at V
OV
 = 72V, values commonly used in Central
Office power distribution applications.
)
(
)
(
)
R3
R3
R2
R1
(typ)
V
V
R3
R2
R3
R2
R1
(typ)
V
V
OVL
OV
UVL
UV
+
+
?/DIV>
=
+
+
+
?/DIV>
=
 
Given V
UV
, V
OV
, and any one of the resistor values,
the remaining two resistor values can be determined.
A suggested value for R3 is selected to provide
approximately 100礎(chǔ) (or more) of current through the
voltage divider chain at V
DD
  = V
UV
. This yields the
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